Sr. Staff Verification Engineer
1 week ago
Responsibilities: Define, develop and optimize comprehensive verification plans and test strategies for digital/mixed-signal IP blocks, subsystems, and full integrated circuits. Work closely with design teams to understand micro-architecture and functional specifications. Create and maintain detailed test plans, coverage models, and verification environments. Drive coverage closure including functional, code, and assertion-based coverage. Generate technical documentation and drive verification reviews. (30%) Design and implement complex testbenches using System Verilog and UVM methodology. Perform block and chip-level register-transfer level (RTL), gate-level and analog/mixed-signal (AMS) verification. Develop directed test cases, constrained-random verification environments and reusable verification components. Debug complex simulation failures and identify root causes in design or verification environments. Improve verification scalability and portability from project to project by environment enhancement and tools automation. Generate and manage continuous integration, regression testing, scoreboards, monitors, and checkers. (30%) Report to remote verification & design teams. Mentor junior verification engineers. (20%) Interface with system, digital hardware, embedded firmware, analog and cross functional teams. (10%) Drive adoption of advanced verification methodologies, best practices and tool evaluation. (5%) Technical support to silicon lab evaluation, test, product and application engineers. (5%) Minimum Qualifications: 8+ years of industry experience in integrated circuit design verification (DV) B.S. or M.S. in Electrical or Computer Engineering Strong analytical, synthesis and problem solving skills In-depth knowledge and experience in digital IC verification for mixed-signal ICs with MCU based hardware systems (ARM, RISC-V, PIC, STM32) with memories, custom digital micro-architecture, interfaces, dedicated hardware peripherals, embedded signal processing, external IPs, and analog peripherals. Proficiency in System Verilog as High-level Verification Language and UVM implementation, Verilog/VHDL, scripting languages (Python, Perl), debugging capabilities, and industry leading EDA verification tools (Synopsys, Cadence, Siemens) Demonstration of technical leadership Experience with standard hardware protocols (I2C, I3C, SPI, MIPI) Independent, self-motivated, rigorous, innovating, team player and able to follow through Excellent verbal and written communication skills Desired Qualifications Knowledge of system-level aspects: signal processing, mixed-signal, digital hardware, embedded firmware, analog, modelling, test and application Experience with analog block behavioral modelling with SV RNM/Verilog/VHDL Experience with consumer and/or ITA market circuit developments
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Sr. Verification Engineer
3 weeks ago
Delhi, India Best NanoTech Full timeSr. Verification EngineerLocation -Bangalore/Pune/HyderabadExperience- 4+ Years RelevantStrong proficiency in SystemVerilog and HDL languages.Hands-on experience with UVM or other industry-standard verification methodologies.Strong object-oriented programming skills using SystemVerilog and C++.Ability to write and interpret architectural/design...
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Staff Engineer, Design Verification
15 hours ago
New Delhi, India Analog Devices Full timeKey ResponsibilitiesStrategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments Verification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality...
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Staff Engineer, Design Verification
2 weeks ago
New Delhi, India Analog Devices Full timeKey Responsibilities Strategic Leadership : Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments Verification Architecture : Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality...
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Staff Engineer, Design Verification
1 week ago
New Delhi, India Analog Devices Full timeKey Responsibilities- Strategic Leadership: Architect and lead verification strategy for complex digital and mixed-signal designs, acting as a key contributor in critical verification environments - Verification Architecture: Design and implement sophisticated UVM-based verification environments that ensure comprehensive test coverage and design quality -...
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Sr. AMS Verification Engineers
3 days ago
New Delhi, India Eximietas Design Full timeEximietas Hiring : Senior AMS Verification Engineers - 4-8 YearsJob Description: Responsibilities: Lead AMS, including reviewing design specifications and defining and executing a verification plan to ensure compliance with specifications. Architect, implement, and automate analog, digital, and AMS test benches to verify pre-silicon designs. Build System...
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Sr. AMS Verification Engineers
15 hours ago
New Delhi, India Eximietas Design Full timeEximietas Hiring : Senior AMS Verification Engineers - 4-8 YearsJob Description:Responsibilities:- Lead AMS, including reviewing design specifications and defining and executing a verification plan to ensure compliance with specifications. - Architect, implement, and automate analog, digital, and AMS test benches to verify pre-silicon designs. - Build System...
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Staff Verification Engineer
1 week ago
New Delhi, India Semtech Full timeResponsibilities: Perform block and chip-level verification in register-transfer level (RTL), gate-level and analog/mixed-signal (AMS). Run digital/mixed-signal simulations as well as formal verification. Work closely with the design team to create verification strategy and detailed verification plan. Develop tests, run regressions and monitor coverage to...
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New Delhi, India ACL Digital Full timeDesign Verification Engineer - Senior / Lead / Sr. LeadLocation: Bangalore / HyderabadExperience: 4 to 10 YearsRequired Qualifications:- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field. - 4+ years of hands-on experience in design verification of high-speed interfaces such as DDR, PCIe, UCIe, or NVMe. -...
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Senior Design Verification Engineer
15 hours ago
New Delhi, India UST Full timeJob Description:As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
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Senior Design Verification Engineer
1 week ago
New Delhi, India UST Full timeJob Description: As a Sr. SoC Design Verification Engineer, you will be responsible for Design for Debug architecture verification related tasks including creating test cases and test bench using UVM methodology. Capacity could include full chip and/or system functional verification with defining verification strategies, methodology and test plan to enable...
