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    Bangalore, India L&T Semiconductor Technologies Full time

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    2 weeks ago

    bangalore, India L&T Semiconductor Technologies Full time

    Role : Physical Design Engineer ( Physical Verification)Experience Level : 5 to 8 yrsThis position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off....

  • Physical design engineer

    2 weeks ago

    Bangalore, India L&T Semiconductor Technologies Full time

    Role : Physical Design Engineer ( Physical Verification) Experience Level : 5 to 8 yrs This position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and...

  • Physical Design Engineer

    2 weeks ago

    bangalore, India L&T Semiconductor Technologies Full time

    Role : Physical Design Engineer ( Physical Verification)Experience Level : 5 to 8 yrsThis position is for a senior-level physical verification engineer who will work on Physical verification of a complex SOC/Cores/Blocks DRC, LVS, ERC, ESD, DFM, Tapeout Work hands-on to solve critical design and execution issues related to physical verification and sign-off....

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    1 month ago

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Physical Design Engineer

2 months ago

Bangalore City, India Tech Mahindra Full time
Hi Folks,Greetings from Tech MahindraWe are hiring for Physical Design EngineerExp: 4-8 yearsLocation: Bangalore/ Kochi/ Vizag / AhmedabadJD:> > RTL to GDS including, Synthesis + PNR
- Fusion compiler / Cadence flow (Innovus)
- Good understanding Macro placement, Floorplanning, placement CTS, Routing
- Design planning (partitioning, bump planning & Routing)
- Very good understanding of STA
- Very good Debugging skill
- Handling atleast 10 member team and driving project
- Understanding about Analog block integration
- Power grid creation
- Low power design> >Signoffchecks
- LEC ( conformal)
- RV (ansys)
- LV (drc clean up – caliber)
- PTPX
- VCLP (vc static checks)
- Caliberlite (intel internal)
- Timing closure (PT ECO/ Tweaker)
- ESD runsTo Apply: Share your resume at