Senior Staff Design Engineer
2 months ago
We're looking for a Senior ASIC Digital Design Engineer to join the team.
Does this sound like a good role for you?
You will be part of the Solutions Group at our Bangalore Design Center, India. This is a Technical Individual Contributor role and offers challenges to work in a multi-site environment on technically challenging IP Cores in the Design & Directed Verification domain.
Job Responsibilities
• Be an individual contributor in the Design Tasks – RTL coding of design, debug, verification coverage improvement in the directed Verilog Test Bench, etc.
• Work on high speed, low latency designs.
• Need to understand Standard Specifications/ the functional specifications/ feature enhancements for the product and create micro-architecture and detailed design documents for some of the components functions/ product features for the DesignWare family of synthesizable cores in protocol areas mainly on High speed Ethernet(100G-1.6T) along with AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI
• Creates deliverables which do not require close review or supervision by a Senior Technical Lead.
• Do technical review of Functional specification, micro-architecture and RTL Code.
• The candidate should be able to analyze the coverage metrics and improve them with definition of additional test cases in directed environment, for features of the protocol/ product specs.
• Create/ work on designs using Low Power Design Methodology and automotive safety.
• The candidate will work in a project and team-oriented environment with teams spread across multiple sites, worldwide.
Key Qualifications and Experience
Must have BSEE in EE with 8+ years of relevant experience or MSEE with 6+ years of relevant experience in the following areas:
• Design of IP Cores or SoC Designs.
• Knowledge of one or more of protocols, AMBA (AMBA2, AXI, CHI)/ SD/eMMC/DDR/PCIe/ USB/ MIPI. Knowledge of High-Speed Ethernet protocol is highly preferred.
• Hands on experience with creating micro-architecture/ detailed design from Functional Specifications for small/ medium design complexity. Must have worked on control path-oriented designs like asynchronous FIFO, DMA architectures, SPRAM/ DPRAM interface design, etc.
• Understanding and prior experience of datapath designs and implementation of arithmetic algorithms such as for FEC etc will be plus
• Hands on experience with Verilog/ System Verilog coding and Simulation tools
• Synthesis flow and static timing flows, Lint, CDC, Formal checking, etc is a must for candidates with design background
• Knowledge of working on high speed and low latency designs.
• Experience with Perforce or similar revision control environment
• Knowledge of Perl/Shell scripts.
• In addition, the candidate should have good communication skills, should be a team player and possess good problem-solving skills.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
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