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Microarchitect & RTL Design Engineer ( Senior Staff / Staff )

3 months ago

bangalore, India Mulya Technologies Full time

Microarchitect & RTL Design Engineer ( Staff / Senior Engineer )


Bangalore / Austin / Santa Clara /

We are an early stage tech startup based in Silicon Valley, funded by top tier venture and strategic investors. We are a team of seasoned semiconductor and software professionals with track record of building successful products and companies. We have offices in Santa Clara and Bangalore and we are actively hiring to build an exceptional team of engineers, architects and executives. We offer generous cash and equity based compensation, an exciting and flexible work environment, and the opportunity to mingle and work with some of the biggest names in the semiconductor industry. While we are always on the lookout for star engineers who are eager to work at a premier startup to build high impact industry transforming products, following are some of the specific roles that are currently open.



Senior Hardware Design Engineer

(US) SANTA CLARA CA, AUSTIN TX, Bangalore

HARDWARE ENGINEERING | ON-SITE

We are seeking a seasoned Hardware Design Engineer with a strong background in microarchitecture and RTL coding. The ideal candidate will play a key role in shaping our technology portfolio, bringing expertise and creativity to our solutions

Responsibilities

  • Design and develop microarchitectures for a set of highly configurable IPs
  • Microarchitecture and RTL coding ensuring optimal performance, power, area
  • Collaborate with software teams to define configuration requirements, verification collaterals etc.
  • Work with verification teams on assertions, test plans, debug, coverage etc.

Qualifications and Preferred Skills

  • BS, MS in Electrical Engineering, Computer Engineering or Computer Science
  • 7+ years and current hands-on experience in microarchitecture and RTL development
  • Proficiency in Verilog, System Verilog
  • Familiarity with industry-standard EDA tools and methodologies
  • Experience with large high-speed, pipelined, stateful designs, and low power designs
  • In-depth understanding of on-chip interconnects and NoCs
  • Experience with in ARM ACE/CHI or similar coherency protocols
  • Experience designing IP blocks for caches, cache coherency, memory subsystems, interconnects and NoCs
  • Familiarity with RAS designs, QoS in fabrics, PCIe/IO is a plus
  • Experience with modern programming languages like Python is a plus
  • Excellent problem-solving skills and attention to detail
  • Strong communication and collaboration skills



Contact: Uday

Mulya Technologies

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