System Verilog and UVM
2 weeks ago
Job Description: VLSI Verification Engineer
Location: Bangalore (Hybrid Work Mode)
Experience: 6 to 15 Years
Salary: Open for Discussion
Job Summary: We are seeking a highly skilled and experienced VLSI Verification Engineer to join our team in Bangalore. The ideal candidate should have extensive hands-on experience with SystemVerilog and UVM. Additionally, expertise in either PCIe or NVMe is mandatory.
Key Responsibilities:
- Develop and implement verification plans using SystemVerilog and UVM methodologies.
- Perform functional verification of complex designs.
- Create and maintain testbenches, simulation environments, and coverage models.
- Debug and resolve design and verification issues.
- Collaborate with design and development teams to ensure comprehensive verification of all features.
Required Skills:
- 6 to 15 years of hands-on experience in VLSI verification.
- Proficiency in SystemVerilog and UVM is mandatory.
- Expertise in PCIe or NVMe is required.
- Strong analytical and problem-solving skills.
- Excellent communication and teamwork abilities.
Preferred Qualifications:
- Experience with scripting languages such as Python or Perl.
- Familiarity with industry-standard verification tools and methodologies.
- Knowledge of digital design and hardware description languages.
Why Join Us:
- Opportunity to work in a cutting-edge technology environment.
- Flexible hybrid work mode.
- Competitive salary package.
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