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Senior Design Verification Engineer
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Senior Design Verification Engineer
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Design Verification Engineer
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Design Verification Engineer
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Design verification engineer
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Design Verification Leader
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Design verification engineer
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Bangalore City, India Client Of Connectpro Full time9+ years of experience in Functional Verification of processors or ASICs.3+ years of experience in the following areas Computer architecture knowledge. Multi-processor Cache Coherency Transport Network on Chip Memory Hierarchy verification. AXI, AHB, ACE, ACE-lite/CHI/On Chip System Fabric interface verification or any other Processor/So C coherency...
Design Verification
2 months ago
- Our world-wide customers are amongst The Who's who in the semiconductor industry. Eteros works not only with some of the top 20 semiconductor startups in the world but boasts of customers who are among the most respected publicly traded semiconductor companies.
- Eteros engineers work on cutting edge technology nodes while working on the state-of-the art designs in the AI/ML, Datacenter, Automotive and 5G domains. Eteros engineers work with some of the brightest, innovative and successful engineers and leaders around the world. A one-of-a-kind opportunity where young Eteros engineers showcase their ability and experience world-wide from day 1 while learning from some of the world's most well-respected companies.
- We are not your traditional design services company offering staff augmentation. Eteros engineers are treated as an integral part of the customer team and routinely are responsible for turnkey, end-to-end ownership and delivery, whether it is Implementation, Digital and Mixed Signal Verification, DFT or Analog Design and Layout. Eteros and our engineers work closely with our customers to define and set methodologies and design flows.
- Eteros invests in our engineers. Our engineers are continuously learning, on and off the job. They are able to grow the breadth and depth of knowledge. We believe in preparing our employees for the fast-track in career development as well as longevity-----------------------------------------------------------------------------Job Title/Role: Power-domain implementation (Low-power/IR-Drop/Reliability) Engineer – Senior/Staff/Sr. Staff EngineerLocation: Bangalore/Hyderabad/AhmedabadExperience Level: 3+ YearsIndustry: SemiconductorsEmployment Type: Full-timeJob Functions: Engineering-----------------------------------------------------------------------------Summary Work on design verification of state-of-the-art SOCs and/or IPs at cutting edge FinFET technology nodes for various customers.This position is for a senior-level Verification engineer who will
- Work on design verification of a complex IPs, Blocks, Sub-systems and SOC-level
- Guide peers, junior engineers working on design verification aspects
- Work hands-on on critical blocks/tasks
- Build/execute SOC verification flows, methodologies and verification of SoCsExperience:
- Understanding of all phases of the IC design process from specification to post-Si
- Design verification of IP-level, SoC -level and/or block-level/sub-system-level designs
- Experience in high-speed, low-power, mixed-signal designs is a plus
- Experience in developing verification plan/verification methodology/flows from scratch
- Hands-on expertise with UMV (or similar) methodology, and Verilog/System Verilog (SV)
- Experience in low-power verification using UPF/CPF power intent flows is a plus
- Experience in constraint-random verification and/or transaction-based verification
- Experience in one or more of the IPs like LPDDR-4&above, PCIE-Gen3&above, SATA, USB 3.0&above, Ethernet, DDR, NVMe, SDMM, MIPI etc.
- Experience with on-chip protocols like AXI/AXI-Lite, AMBA/AHB/APB etc.
- Experience with gate-level simulations - timing/no-timing, SDF annotation
- Experience in developing one or more of - monitors, sequencers, drivers, scoreboards, checkers, coverage analysis/metrics, coverage closure, assertions, VIP components etc.
- Strong scripting skills with C/C++/Perl/Python
- Understanding of emulations platforms, S/W co-development, end-to-end verification
- EDA Tools: Industry standard tools from Synopsys, Cadence, Mentor etc. Qualifications:
- BTech/MTech/PhD with 3-10 years’ experience in ASIC/SOC/IP design verification
- Proven track record with multiple successful ASIC/SOC design verification projects
- Proven ability to independently deliver results in a very fast-moving start-up environment, be able to work hands-on as and when needed
- Be able to work under limited supervision and take complete accountability.
- Excellent written and verbal communication skills What's in it for you
- Work on leading edge technologies
- An opportunity for career development and growth
- Competitive compensation & Exceptional benefits
