Senior DFT Engineer

1 week ago

pune, India People Impact Full time

We are seeking an experienced Senior Design for Test (DFT) Engineer to join our dynamic team. The ideal candidate will have 5-10 years of proven industry experience in DFT methodologies and techniques. As a Senior DFT Engineer, you will be responsible for developing and implementing DFT strategies to ensure the highest quality and testability of our integrated circuit (IC) designs.

Key Responsibilities :

- Develop DFT architectures and methodologies for complex digital designs.

- Collaborate with design and verification teams to integrate DFT features into ASIC designs.

- Implement scan insertion, ATPG (Automatic Test Pattern Generation), and memory BIST (Built-In Self-Test) techniques.

- Define and execute DFT verification and validation plans.

- Optimize test patterns for test time reduction and minimal hardware overhead.

- Analyze and debug DFT-related issues during silicon bring-up and production testing.

- Stay updated with the latest DFT trends, tools, and methodologies.

Required Skills and Qualifications:

- Bachelor's or Master's degree in Electrical Engineering or related field.

- 5-10 years of hands-on experience in DFT for ASIC and/or FPGA designs.

- Proficiency in industry-standard DFT tools such as Synopsys Tetramax, Mentor Tessent, or Cadence Encounter Test.

- Strong understanding of scan, ATPG, JTAG, and other DFT techniques.

- Experience in DFT verification, including gate-level simulations and timing analysis.

- Familiarity with scripting languages (e.g., Perl, Python) for automation tasks.

- Excellent problem-solving and analytical skills.

- Ability to work effectively in a team environment and communicate technical concepts clearly.

Preferred Qualifications :

- Experience with low-power DFT techniques.

- Knowledge of post-silicon debug and yield analysis.

- Familiarity with analog and mixed-signal DFT concepts.

Location - Noida, Bangalore, Hyderabad, Pune

(ref:hirist.tech)

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