SoC Analog and Mixed Signal Verification
3 weeks ago
Key Responsibilities:Power Management verification – Creating a test plan for all the various power protocols like power-up of chip, power sequencing, low power mode entry exit, different voltage detects and POR generation and many other such featuresData Acquisition System Verification – Includes the verification integration and functionality of entire sub-system of ADC and DAC. Verifying all various architecture of ADCs like SAR, Sigma-Delta, Cyclic and checking its interface with GPIOs, MCU etc.Clocking System Verification – Includes the verification of integration and verification of clocking blocks like PLL, RC-Oscillators, Crystal Oscillators etc.Power Electronics System verification – Include the verification of integration and functionality of power electronics sub-systems like high power actuator switches, motor drives and any other drives on the SoC.Verification Infrastructure– Creating Verilog-A/AMS models for writing monitors and drivers that can be used in the verification of power management protocols for the entire SoC.Coordinate with other departments, such as Analog IP Teams, Functional Integration teams and the Digital verification teams to ensure cohesive project execution.
Please note that the above key areas of responsibilities are not exhaustive. Management reserves the right to assign additional responsibilities as deemed necessary to meet the evolving needs of the company.
Qualifications –B.Tech/Mtech or equivalent courses and Industry experience with below requirements–10+ years of experience in Analog and Mixed Signal verification at IP, sub-system at SoC levelGood understanding of Analog and mixed-signal architecture, designs and protocols, of power management, data acquisition, clocking, IO etcHands-on experience in verifying the SoC/IP level AMS blocks where the analog blocks interact with a digital block. The analog blocks could be – LDO, DC-DC Converter, SAR ADC, Sigma-Delta ADC, PLL, Cystal Oscillators, RC Oscillators, Analog IOs, GPIOs with Input/Output buffer enables, open-drain configurations etcHands-on experience of SoC/IP/Sub-system level AMS Testbench creation using SPICE and Verilog-AMS protocols that can be clubbed with standard Digital testbenches designed with Verilog/SystemVerilog, UVM etcExposure to post-silicon analysis, debug and signoff of Analog blocks, working with Analog Validation/Bench teams, analysing various silicon level signatures, figuring out if features are correct as per specs and signing off characterization data
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