Senior Analog and Mixed Signal Verification Engineer
4 weeks ago
Job Summary:
We are seeking a highly skilled and experienced SoC Analog and Mixed Signal Verification Engineer to join our team at L&T Semiconductor Technologies. The successful candidate will be responsible for verifying the analog and mixed-signal blocks of our SoC designs, ensuring that they meet the required specifications and standards.
Key Responsibilities:
- Power Management Verification: Create test plans for various power protocols, including power-up, power sequencing, low power mode entry and exit, voltage detection, and POR generation.
- Data Acquisition System Verification: Verify the integration and functionality of ADC and DAC sub-systems, including various ADC architectures such as SAR, Sigma-Delta, and Cyclic.
- Clocking System Verification: Verify the integration and functionality of clocking blocks, including PLL, RC-Oscillators, and Crystal Oscillators.
- Power Electronics System Verification: Verify the integration and functionality of power electronics sub-systems, including high power actuator switches, motor drives, and other drives on the SoC.
- Verification Infrastructure: Create Verilog-A/AMS models for writing monitors and drivers that can be used in the verification of power management protocols for the entire SoC.
- Collaboration: Coordinate with other departments, such as Analog IP Teams, Functional Integration teams, and Digital verification teams to ensure cohesive project execution.
Requirements:
- B.Tech/Mtech or equivalent courses and industry experience with 10+ years of experience in Analog and Mixed Signal verification at IP, sub-system, and SoC level.
- Good understanding of Analog and mixed-signal architecture, designs, and protocols, including power management, data acquisition, clocking, and IO.
- Hands-on experience in verifying SoC/IP level AMS blocks where analog blocks interact with digital blocks, including LDO, DC-DC Converter, SAR ADC, Sigma-Delta ADC, PLL, Crystal Oscillators, RC Oscillators, Analog IOs, GPIOs with Input/Output buffer enables, and open-drain configurations.
- Hands-on experience of SoC/IP/Sub-system level AMS Testbench creation using SPICE and Verilog-AMS protocols that can be clubbed with standard Digital testbenches designed with Verilog/SystemVerilog, UVM, etc.
- Exposure to post-silicon analysis, debug, and signoff of Analog blocks, working with Analog Validation/Bench teams, analyzing various silicon level signatures, figuring out if features are correct as per specs, and signing off characterization data.
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