Lead PnR Engineer

3 weeks ago

HyderabadDelhi NCR, India SILCOSYS Solutions Pvt. Ltd Full time

Job Description :


We are looking for a highly skilled and experienced Lead PnR Engineer with 7 to 10 years of experience to join our dynamic team. The ideal candidate will have extensive experience in physical design, specifically in place and route for complex ASICs and SoCs.

This role requires a deep understanding of the entire PnR flow, including floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification.

Key Responsibilities :

- Leadership and Mentorship : Lead and mentor a team of PnR engineers, providing technical guidance and support to ensure successful project execution.

- PnR Implementation : Oversee and execute the entire place and route flow, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.

- Timing Closure : Ensure timing closure using advanced static timing analysis (STA) techniques and tools.

- Power and Area Optimization : Optimize designs for power, performance, and area, considering factors such as power gating, multi-Vt cells, and clock gating.

- EDA Tools Proficiency : Utilize industry-standard EDA tools such as Cadence Innovus, Synopsys ICC2, and Mentor Graphics Calibre for physical design and verification.

- Design Rule Compliance : Ensure compliance with foundry-specific design rules and constraints, including DRC (Design Rule Check) and LVS (Layout Versus Schematic).

- Collaboration : Work closely with RTL design, DFT, and verification teams to resolve design issues and ensure seamless integration.

- Documentation : Maintain comprehensive documentation of PnR design methodologies, scripts, and workflows.

- Process Improvement : Contribute to the development and enhancement of physical design methodologies and flows.

- Tape-out : Lead the tape-out process, ensuring that all design criteria and project timelines are met.

Required Qualifications :

- Education: Bachelor's or Master's degree in Computer Science or a related field.

- Experience: 7 to 10 years of hands-on experience in physical design, with a focus on place and route.

Technical Skills :

- Proficiency in using physical design tools such as Cadence Innovus, Synopsys ICC2, and Mentor Graphics Calibre.

- Strong understanding of ASIC and SoC design flow, including synthesis, floorplanning, placement, CTS, routing, and physical verification.

- Experience with static timing analysis (STA) tools like Synopsys PrimeTime.

- Familiarity with power analysis and optimization tools and techniques.

- Knowledge of scripting languages (TCL, Perl, Python) for automation of design tasks.

(ref:hirist.tech)

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