Lead PnR Engineer

7 days ago


Delhi, Delhi, India SILCOSYS Solutions Pvt. Ltd Full time

Job Description:

We are in search of a highly skilled Lead PnR Engineer with 7 to 10 years of experience to join our team.

The ideal candidate should have significant experience in physical design, particularly in place and route for complex ASICs and SoCs.

This position demands a profound grasp of the entire PnR process, covering floorplanning, placement, clock tree synthesis, routing, timing closure, and physical verification.


Key Responsibilities:

  • Leadership and Mentorship: Guide and support a team of PnR engineers, offering technical expertise for successful project completion.
  • PnR Implementation: Supervise and carry out the complete place and route process, encompassing floorplanning, placement, clock tree synthesis (CTS), routing, and optimization.
  • Timing Closure: Implement advanced static timing analysis (STA) techniques and tools to achieve timing closure.
  • Power and Area Optimization: Optimize designs for power, performance, and area, considering factors like power gating, multiVt cells, and clock gating.
  • EDA Tools Proficiency: Utilize standard EDA tools such as Cadence Innovus, Synopsys ICC2, and Mentor Graphics Calibre for physical design and verification.
  • Design Rule Compliance: Ensure adherence to foundry-specific design rules and constraints, covering DRC (Design Rule Check) and LVS (Layout Versus Schematic).
  • Collaboration: Partner closely with RTL design, DFT, and verification teams to address design issues and ensure smooth integration.
  • Documentation: Maintain detailed documentation of PnR design methodologies, scripts, and workflows.
  • Process Improvement: Contribute to refining and advancing physical design methodologies and processes.
  • Tapeout: Lead the tapeout process, guaranteeing alignment with design requirements and project schedules.

Required Qualifications:

  • Education: Bachelor's or Master's degree in Computer Science or a related field.
  • Experience: 7 to 10 years of practical experience in physical design, emphasizing place and route.

Technical Skills:

  • Proficiency in physical design tools such as Cadence Innovus, Synopsys ICC2, and Mentor Graphics Calibre.
  • Comprehensive understanding of ASIC and SoC design flow, encompassing synthesis, floorplanning, placement, CTS, routing, and physical verification.
  • Experience with static timing analysis (STA) tools like Synopsys PrimeTime.
  • Familiarity with power analysis and optimization tools and techniques.
  • Knowledge of scripting languages (TCL, Perl, Python) for automating design tasks.


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