Rtl Design Engineer

2 months ago


Ibrahim Bagh Lines, India BITSILICA Full time

Experience range : 4+ Yrs and above only(no freshers please)Work Location : HyderabadNotice : Immediate to 15 days Job Scope: RTL development from micro-architectureSoC, Memory, Peripheral, Security and Cache IP’s Analysis & IntegrationRTL Quality checks (VCS, synthesis checks, LINT, LEC, CDC)Failures Debug/Bug fixes on RTL and NetlistLow level design document generation, implementation & reviewARM Cortex based system understanding & Integration.DFT needs: ATPG pattern generation, low pin count implementation, coverage analysis and improvement.DFT needs: MBIST wrapper generation and verification, memory repair.DFT needs : debug interface (JTAG, Serial wire debug for ARM)DFT needs: Scan constraints development and support for implementation.Please share resumes to


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