Rtl Principal Design Engineer

1 day ago


Bangalore City, India Cadence Design Systems Full time

Be part of the Cadence High-Speed SerDes PHY IP Front end Design team responsible for - -Defining microarchitecture of digital blocks involving microcontroller-based designs to meet specifications, optimized for performance metrics of timing, area, and power.-Lead and also hands-on end-to-end ASIC design including RTL implementation and design processes of Lint/CDC/SDC definition/STA/Synthesis.-Collaborate with cross-functional teams of Architecture, Verification, Physical Design, and Mixed Signal teams.-Mentor junior members of the team.-Drive high-performance team culture of discipline, agility, and excellence. Requirements :Education: Bachelors in Electronics Engineering with +7 years, or Masters +5 years, or Ph.D. + 2 years of relevant experience in Digital Design.Hands-on experience in micro-architecting digital blocks and RTL implementation in Verilog/SV.Hands-on experience in SDC definition, STA, Lint Checks, CDC, Synthesis, and trail PNR.Desired Protocols knowledge – Ethernet, USB, PCIe, MIPI(DPHY), HDMI/DisplayWorking closely with Analog design teams to co-develop algorithms, develop interfaces, and modeling in Verilog RLM as well as design high-speed critical digital circuits and signal processing (DSP) blocks.



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