Physical Design Manager
4 months ago
KEY RESPONSIBILITIES:Manage the team responsible for Synthesis, Physical Design, timing and Physical closureManage a large team of internal and external resourcesResponsible for ensuring the completion of the SOC chip on schedule with high QORPhysical implementation of block level and subsystem levelContribute to Synthesis, Power Reduction, Timing Convergence Floorplan efforts of block and subsystem
PREFERRED EXPERIENCE:Proven track record on successfully managing PD teams for complex SOCHave an in depth understanding and experience for all Physical Design activities for a large, leading technology SOC ASIC chipHave strong management, technical problem solving, communication and presentation skillsGreat team player able to effectively interact and collaborate partner teamsExperienced with Front-End design, DFX and Physical Design FlowsCommunication skills: excellent oral, written and presentation skillsExtensive Experience in handling different PNR tools - Synopsys ICC2, ICC, Design Compiler, PrimeTime, StarRC, Mentor Graphics Calibre, Apache RedhawkPhysical Implementation of Power-plan, Synthesis, Placement, CTS, Timing Closure, Routing, Extraction, Physical Verification (DRC LVS), Crosstalk Analysis, EM/IRHands on experience on 7nm and sub-7nm projectsExperienced in Full Chip Floorplaning, PNR Partitioning / Bump Placement is preferredExperience in Low power and high-performance design.Responsible for on-time delivery of block-level layouts with exceptional quality.Strong self-driving ability & problem-solving skills with high drive for improvementsShould have excellent communication skills (both written and oral)
ACADEMIC CREDENTIALS:BE/B.Tech/ME/M.TECH or equivalent ECE/EEE12+ years of experience in Physical Design with at least 3+ years of experience in people management
Contact:UdayMulya "Mining The Knowledge Community"
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