Physical design engineer

1 week ago


Delhi, India Jones RecruitZo Full time
Job Title: Senior ASIC Design Engineer (Physical Design & Timing Optimization)
Location: WFO / Hyderabad)
Experience: 5-8 Years
Notice Period: 30- 45 days
Job Description:
We are looking for a skilled Senior ASIC Design Engineer with expertise in Physical Design and Timing Optimization. The ideal candidate will have hands-on experience with Hierarchical and Block-level Physical Aware Synthesis , timing closure , and ASIC backend design flows. You’ll work on floor planning, place & route (Pn R), clock tree synthesis (CTS) , and power analysis , while developing timing constraints and supporting low-power design.
Key Responsibilities:
Lead timing closure and physical optimization for ASIC designs.
Develop timing constraints and provide support to the Physical Design (PD) team.
Implement low power design using UPF , and perform power-aware checks.
Perform clock-domain crossing checks , LEC , and manage functional ECOs.
Work with advanced process nodes (3nm, 7nm, 14nm) and custom layout design using Cadence Virtuoso.
Required Skills:
5-8 years of experience in ASIC backend design and timing optimization.
Strong background in physical design , timing constraints , low power design , and ECO generation.
Experience with Cadence Virtuoso , HDL-Verilog , and ASIC design flows for advanced nodes.
If you're passionate about ASIC design and timing optimization , apply now

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