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Engineer, Design Verification
4 months ago
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End to End verification ownership of IP or Subsystem or SOC level
Verification of complex microprocessor designs, neural nets and high-speed peripherals using leading edge verification methodologies.
UVM testbench architecture development and implementation of DV flows, methodology
Defining testplans, tests and verification methodology for block / subsystem and chip-level verification. Working with the design team in generating and reviewing testplans and closure of code and functional coverage
Working with other verification team disciplines like emulation, FPGA and Firmware teams to determine correct functionality.
Formal verification of IP’s and Subsystems
NOC, Interconnect verification
Performance verification and Performance analysis of complex SOCs end to end scenarios
System level use case scenarios definition, coding and verification
Innovating verification solutions to hit deliverable schedules.
The chance to be exposed to and learn state of the art verification techniques such as formal, emulation, portable stimulus and virtual platforms.
Come up with verification strategy for a product after going through product requirements and design specifications.
B.Tech/M.Tech with 3+ years of industry experience in Digital Pre-Silicon verification.
Good understanding of SOC/Subsystem design concepts and design architectures.
Hands on experience in developing, updating and debugging of Verilog, SV-UVM, SOC level testbenches is a must.
Experience in closing the verification of block, subsystem level verification using industry standard metrics like code and functional coverage is a must.
Expertise on NOC, Bus and Interconnect Verification. Coverage Analysis and improvements
Test Bench, TB, environment, architect and implement verification flow and methodology.
Power aware verification with UPF, Power analysis and Power optimization
Knowledge on Formal verification is an added advantage.
Gate level Simulation with timing annotated
Strong knowledge of test-plan generation, coverage analysis transaction level modeling, pseudo and constrained random techniques with System Verilog
In-depth knowledge of SV-UVM and debugging of testbenches is a must.
Assertion and formal knowledge is an advantage.
Knowledge of microprocessor cores such as ARM, RISC-V, Tensilica, Neural Network, GPU Cores is a plus.
System Verilog, C/C++, System C, TCL/Python/shell-scripting
Exceptional interpersonal and communication skills, collaborate and influence innovative design development/verification methodologies to wider team spread across the globe.
Quick to adopt new technologies with good problem-solving skills.
Job Req Type: ExperiencedRequired Travel: Yes, 10% of the timeShift Type: 1st Shift/Days
