VLSI - Synthesis and Static Timing Analysis - Senior Design Engineer
1 month ago
-----------------------------------------------------------------------------Job Title/Role: Synthesis and Static Timing Analysis - Senior Design EngineerLocation
: Bangalore/Hyderabad/AhmedabadExperience
Level
: 3+ YearsIndustry
: SemiconductorsEmployment
Type
: Full-timeJob
Functions
: Engineering-----------------------------------------------------------------------------SummaryJoin a development team and lead the synthesis, static timing and DFT efforts for an advanced mixed signal chip for a high-profile Silicon Valley startup.In this highly visible role, as part of a highly talented team you will be at the heart of the Soc design effort interfacing with all disciplines with critical impact in getting functional products to of customers quickly. As a Sr, ASIC STA Engineer, you will be a part of the SOC digital design team responsible for providing integrated solutions into a growth industry
Key QualificationsThe position requires thorough knowledge of the ASIC design timing closure flow and methodology.• BTech/MTech/PhD with at least 4+ years hands-on experience in ASIC timing constraints generation and timing closure.• Expertise in STA tools (Tempus and Primetime) and methodologies for timing closure with a good understanding of OCV, noise and crosstalk effects on timing.• Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced finFET technology nodes, preferably 7nm.• Knowledge of timing corners/modes and process variations.• Knowledge of low-power techniques including clock gating, power gating and millivoltage designs. Proficient in scripting languages (Tcl and Perl).• ECO timing flow• Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).• Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools.• Must be able to solve complex problems and independently drive tasks to completion in a timely manner.• Be able to work under limited supervision and take complete accountability.
Responsibilities Include• Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).• Develop and maintain methodology and flows related to timing verification and closure.• Generation of block and full chip timing constraints.• Analyze timing reports and utilize scripting techniques to develop insights and drive rapid Eteros Technologies, Inc. Confidential Sep 2020 timing closure.• Support digital chip integration work and flows
What's in it for you• Work on leading edge technologies• An opportunity for career development and growth• Competitive compensation• Medical Benefits and more
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delhi, India Eteros Technologies Full timeCompany: Eteros Technologies India Private LimitedEteros Technologies, Inc. is a Semiconductor Engineering services startup, head quartered in the heart of the Silicon Valley, San Jose, CA, USA. Eteros Technologies India Pvt Ltd is a wholly owned subsidiary offices in Bangalore, Noida, Hyderabad and Ahmedabad• Our world-wide customers are amongst The Who's...
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