Staff Engineer – ASIC Digital Design(DDR PHY)
4 months ago
Experience Required:
6 - 11 Years
Job Term:
Permanent
Location:
Bangalore
Category:
Semiconductor Design
World leader in innovative memory solutions
JOB Description:
•To be part of a highly skilled and challenging high speed parallel PHY such as DDR, LPDDR etc design team.
•Design and develop high speed interface PHY and its sub-block such as high speed data paths, analog calibration, training, IP initialization, low power control, test, loopback etc
•Responsible for various aspects of design and verification from spec to silicon along with interface design for controller and SoC.
•Active involvement in problem solving and implementing opportunities for improvement
•Mentoring and coaching other design team members on technical issues
•Pair with Analog designers to ensure smooth interface between Digital and Analog circuits
•Equal opportunity position with excellent pay package
SKILLS required:
•Strong fundamental knowledge of digital design, Verilog and scripting languages
•Experience with micro-architecture and Asynchronous digital designs
•Working knowledge of Synthesis, STA, Lint & CDC
•Working knowledge of DDR/LPDDR JEDEC protocol and DDR PHY designs
•Experience with DDR training algorithms and data path designs
•Experience in domain transfer designs, APB/JTAG, DFI
•M.S./M.Tech, BS/BE (Electronics)
Experience Required: 7+ Years
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