RTL - Tech Lead
2 weeks ago
RTL -Tech Lead. Experience: 7 to 9 years’ experience. Educational Qualification: Engineering degree in E&C Location: Bangalore Job Description: Define DSP, System and Board architecture. Create proposal for new project enquiries Experience in handling the team. Partition the algorithms for implementing in FPGA and/or in SW. Identify the building blocks & Signal Processing functions. Provide estimates on FPGA resources, computation bandwidth, and memory bandwidth. Create module level details from architecture, coding, simulation and perform peer reviews. Define, create and maintain all project related documentation, especially design documents with detailed analysis reports. Provide support to customer during integration phases at test sites and support to production teams Creating SRS, ATP for the system Apply the methodologies for design, verification or validation Provide support to customer during integration phases at test sites Defining the architecture of RTL functions, partitioning algorithms HDL Coding, review Simulation and Implementation Testing on board and debugging Project ownership including identifying risks, dependencies, tracking project schedule, discussions with customers, design reviews. Supervise and mentor at least 2 to 3 DE/SDEs Team Management Professional Skills: · Proficiency in VHDL · Xilinx tools for synthesis and implementation · Thorough understanding of Xilinx FPGA’s · Functional and Timing Simulation · Hardware Design : Logic Design & Debugging expertise · FPGA Design : VHDL/Verilog RTL Coding, System C/ System Verilog · FPGA Design : FPGA Synthesis & PAR Tools · Fluency, good communication & presentation skills. · Configuration/Version control tools like SVN. · Knowledge on sRIO, PCIe, Ethernet and other protocols. Desired Skill Set: · Implementing DSP algorithms in FPGA environment for Radar and Electronic Warfare systems. · Interact with SW and HW teams to define the architecture/system partitioning · FPGA development flow: micro-architecting, RTL coding, Synthesis & implementation flow, verification and validation. · Modeling the algorithms in Octave/MATLAB, generating test vectors, visualizing data. · Converting floating point modules to FPGA friendly fixed point modules. · Familiarity with DSP Xilinx IP cores and customization options : FFT, FIR, DDC, NCO etc., · Thorough knowledge on interfacing with ADCs and DACs and interpreting their performance. · Transferring data from FPGA over sRIO, PCIe, Ethernet and other protocols. · Configuration/Version control tools like SVN
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Lead rtl design engineer
3 days ago
Bengaluru, India ACL Digital Full timeLead RTL Design EngineersExperience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and Bangalore Basic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification,...
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Lead rtl design engineer
5 days ago
Bengaluru, India ACL Digital Full timeLead RTL Design EngineersExperience Level:10+ years of RTL design and development Job Description: Silicon Design Engineer Location: Hyderabad and Bangalore Basic Job Deliverable: Silicon Design Engineer (RTL Design and Development) o Responsible for RTL design and development o Responsible for generating documents, such as requirements specification,...
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RTL Lead
4 weeks ago
Bengaluru, India IT Firm Full timeRole : RTL LeadExperience : 8 - 12 YearsLocation : Bangalore & HyderabadJob Description : - SoC RTL Design Engineer with 8 - 12 years experience- Expertise in writing RTL in Verilog and System Verilog- Experience in ARM Architecture based SoC design- Knowledge of ARM based bus protocols like CHI, AXI, AHB, APB, PCIe is must- Hands-on experience in...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of SoC flows.Primary Skills:VHDL,...
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RTL Design Lead
7 days ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of SoC flows.Primary Skills:VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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Rtl design lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of so C flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, Spy Glass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of So C flows.Primary Skills:VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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Rtl design lead
7 days ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of so C flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, Spy Glass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of So C flows.Primary Skills:VHDL,...
