RTL Lead
4 weeks ago
Role : RTL LeadExperience : 8 - 12 YearsLocation : Bangalore & HyderabadJob Description : - SoC RTL Design Engineer with 8 - 12 years experience- Expertise in writing RTL in Verilog and System Verilog- Experience in ARM Architecture based SoC design- Knowledge of ARM based bus protocols like CHI, AXI, AHB, APB, PCIe is must- Hands-on experience in integration of PCIe and Ethernet IPs, chio IO integration- Hands-on experience in design static checks like Lint, CDC, RDC, CLP, UPF etc- Working knowledge of GIT is preferred- Education : Master's degree or equivalent in EE or Computer Engineering (CE)- Excellent analytical, and problem-solving skillsMandatory skills :- Any candidate with PCIE/USB/Ethernet experience is good. If not, then any RTL design profile will also be ok.- Prior experience with Lint, CDC STA, UPF, CLP tools is must.Note : - Candidates with 8 - 12 years should have the following skills.- Should have good understanding of SoC design flows- Good technical leadership skills with ability to guide the team members on SoC execution- Expertise in SoC architecture and mapping the architecture spec to implementation level details- Excellent communication skills is a must (ref:hirist.tech)
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RTL Design Lead
7 days ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of SoC flows.Primary Skills:VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of SoC flows.Primary Skills:VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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RTL Design Lead
7 days ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows.Primary Skills: VHDL,...
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Rtl design lead
6 days ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of so C flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, Spy Glass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of So C flows.Primary Skills:VHDL,...
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Rtl design lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | BangaloreShould be good in Integration of SOC & RTL coding.Should be aware of so C flow like Spyglass-Lint/Synthesis (DC)/CDC.Should be aware of scripting language.Candidate should have experience on SOC Integration, Spy Glass Lint, CDC, DC-Synthesis & VCLSP.Should have good understanding of So C flows.Primary Skills:VHDL,...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
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RTL Design Lead
1 week ago
Bengaluru, India Capgemini Engineering Full timeRTL Design Lead| 6 to 12 Years | Bangalore Should be good in Integration of SOC & RTL coding. Should be aware of soC flow like Spyglass-Lint/Synthesis (DC)/CDC. Should be aware of scripting language. Candidate should have experience on SOC Integration, SpyGlass Lint, CDC, DC-Synthesis & VCLSP. Should have good understanding of SoC flows. Primary Skills:...
