ASIC verification engineer
1 month ago
- Required ASIC/RTL design verification engineer
- Experience:- 3-10 yrs
- Notice period:- immediate to 90 days
- Salary:- as per company
- Skills- Strong knowledge of SV and UVM
The purpose of the role is to develop modules in the company's next generation of ASICs for Radio equipment and Radio Access Network computing.
This module performs advanced signal processing. This role includes test bench systemization, UVM test case development, verification, and product documentation.
Required skills:
• UVM Verification
• ASIC Verification
• System Verilog
• Scripting
• Verification
• Product documentation
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