
Senior Design Verification Engineer
4 weeks ago
We're Hiring – Design Verification Engineers (Bangalore)
ACL Digital is looking for strong Verification Engineers to join our client's team at Bangalore. If you have hands-on expertise in SystemVerilog, UVM, Debug, Processor/DSP subsystems , we want to hear from you
Senior Design Verification Engineer – DSP / Processor Subsystem
Location: Bangalore
Notice Period: Immediate to 20 Days only
Experience: 4 – 10 Years
Responsibilities
- Develop and execute test cases and regressions for DSP/Processor subsystems.
- Perform performance analysis for DSP/NPU workloads.
- Work on coverage closure, regressions, and debug at IP/Subsystem level.
- Collaborate with architecture, design, and software teams .
- Develop C-based verification flows along with SV/UVM-based environments .
Requirements
- Strong in SystemVerilog & UVM .
- C-based verification experience (processors).
- Knowledge of DSP architectures / Neural Network Engines (NNE) .
- Performance verification expertise (latency/throughput).
- 4+ years of IP/Sub-system DV experience .
Senior Design Verification Engineer – Debug Subsystem
Location: Bangalore
Notice Period: Immediate to 30 Days only
Experience: 4 – 10 Years
Responsibilities
- End-to-end Debug Subsystem Verification (trace, crash debug, visibility fabric).
- Define and execute Verification Plans (VPlan) .
- Perform RTL DV, GLS, regression automation, and coverage closure .
- Collaborate with SW & Architecture teams for debug feature validation.
- Support ARM CPU debug infrastructure verification (CoreSight) .
Requirements
- Strong in SystemVerilog, UVM, RTL DV, GLS .
- Understanding of ARM CoreSight Debug Architecture .
- ARM CPU debug methodologies (trace, crash debug).
- Strong knowledge of C programming + scripting (Python/Perl).
- 4+ years of relevant verification experience .
Apply Now:
WhatsApp for quick connect:
Notice Period: Immediate to 20 Days only
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