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Asic Design Engineer
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Asic Design Engineer
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Asic Rtl Design Leads
4 months ago
Bangalore City, India Wipro Full timeHi All,We are Hiring ASIC RTL Design Engineers / Leads.Location: INDIA.Work Mode: Hybrid.Experience: 3 20 Yrs.Expertise in SoC/IP design.* Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.* In depth knowledge on RTL quality checks (Lint, CDC).* Knowledge of synthesis and low power is a plus.* Good understanding...
Asic RTL Design Engineer
3 months ago
Requirements
- Expertisein SoC/IPdesign.
- Expertisein IP design Subsystem/Cluster and SoC level integration usingVerilog/SystemVerilog.
- Indepth knowledge on RTL quality checks (LintCDC).
- Knowledgeof synthesis and low power is aplus.
- Goodunderstanding of AMBA bus protocols (AXI AHB ATBAPB).
- Goodunderstanding of timingconcepts.
- Knowledgeof one or more of the interface protocols like PCIe DDR EthernetI2C UARTSPI.
- Expertisein setting up and using tools like Spyglass Lint/CDC Synopsys DCVerdi/Xcellium
- Understandingof scripting languages like Make flow Perl shell pythonetc.
- Understandingof processor architecture and/or ARM debug architecture is aplus.
- Ableto help and debug issues for multiplesubsystems.
- Ableto create/review design documents for multiplesubsystems.
- Ableto support physical design verification DFT and SW teams on designqueries and reviews.
- Bachelorsdegree in electrical engineering Computer Engineering or relatedfield
- 3to 10 years of experience as Asic RTL DesignEngineer
Expertise in SoC/IP design. Expertise in IP design,Subsystem/Cluster and SoC level integration using Verilog/SystemVerilog. In depth knowledge on RTL quality checks (Lint, CDC).Knowledge of synthesis and low power is a plus. Good understandingof AMBA bus protocols (AXI, AHB, ATB, APB). Good understanding oftiming concepts. Knowledge of one or more of the interfaceprotocols like PCIe, DDR, Ethernet, I2C, UART, SPI. Expertise insetting up and using tools like Spyglass Lint/CDC, Synopsys DC,Verdi/Xcellium Understanding of scripting languages like Make flow,Perl, shell, python etc. Understanding of processor architectureand/or ARM debug architecture is a plus. Able to help and debugissues for multiple subsystems. Able to create/review designdocuments for multiple subsystems. Able to support physical design,verification, DFT and SW teams on design queries and reviews.Bachelor's degree in electrical engineering, Computer Engineering,or related field 3 to 10+ years of experience as Asic RTL DesignEngineer
