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Senior Verification Engineer
3 weeks ago
What You Will Do·Define overall verification strategies, methodologies, and simulation environment·Work with RTL designers, system architects and block level verification engineers to develop top level verification requirements and test plans based on specifications.·Develop, maintain and publish verification specifications.·Analyze and debug simulation failures·Generates code coverage and functional coverage report·Run gate level simulation and debug them.·Perform the constraint assertion-based verificationWho You Are (Basic Qualifications)·BS in EE with 3+ years of experience or MS in EE with 1+ year experience·Strong knowledge with ASIC Simulation Tool & Verification Language: all sign-off simulators, Verdi/Siloti·Fluent in verification language such as
UVM/OVM/System Verilog, Vera, Verilog·Experience in writing Test-plans and creating directed and random test cases·Strong scripting skills in
Perl, Python, Linux shells etc
Who We AreAt Koch companies, we are entrepreneurs. This means we openly challenge the status quo, find new ways to create value and get rewarded for our individual contributions. Any compensation range provided for a role is an estimate determined by available market data. The actual amount may be higher or lower than the range provided considering each candidate's knowledge, skills, abilities, and geographic location. If you have questions, please speak to your recruiter about the flexibility and detail of our compensation philosophy.
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