Senior Formal Verification Engineer

2 days ago

Bengaluru, India Pure Silicon Solutions Full time

As a Senior Engineer in Formal Verification, you will be responsible for designing, developing, and implementing verification environments using Formal Verification.


Responsibilities, Requirements, and Qualifications

Work on leading-edge ASICs/SoCs or key design IPs with US-based Top Customers.

  • Bachelor's or Master's Degree in Electrical/Electronics/Computer Engineering or a related field
  • 5+ years of hands-on experience in silicon architecture, design, or verification is a MUST
  • 3+ years of hands-on experience in Formal Verification, developing and implementing formal verification environments
  • Implement and improve functional verification in semiconductor IP and design blocks.
  • Develop test plans and verification methodologies to verify the microarchitecture and design
  • Strong understanding of Formal Verification using SystemVerilog Assertions.
  • Experience in logic and SoC Verification from planning to closure
  • Good understanding of verification flows and tools, especially Formal Verification tools.
  • Experience in at least one industry-standard formal verification tool (such as Cadence Jasper Gold, Synopsys VC Formal, or Siemens Questa Formal)
  • Demonstrated expertise in Digital Logic Design and Computer Architecture
  • Excellent problem-solving skills and ability to work in a team environment
  • Prior hands-on work experience in Control and Data Path verification using FV
  • Excellent verbal and written communication skills.
  • An ability to interact with customers to understand their requirements and deliver high-quality code is expected.

Other Relevant Information

Reports to the VP of Engineering.

Great visibility. Competitive salary and generous performance bonus.

Opportunity to move to and work on projects in the US for select candidates after 12-24 months

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