FPGA Compilation Flow Expert

2 weeks ago

Hyderabad, India ACL Digital Full time

Job Description: Vivado Backend Location : Hyderabad Experience : 4 years An experienced application engineer to focus on FPGA & ACAP Compilation flows, design closure ease-of-use, tools specification, validation, documentation, and key customer’s support Open Position1 No. Basic Job Deliverable: - Contribute to triaging reported issues in several Vivado product areas, such as design entry, synthesis, implementation, and help engineering address them effectively. - Actively explore innovative methodologies and their impact on flow and design practices, with emphasis on timing closure and compile time, as well as productivity with the new Versal ACAP family. - Develop and deliver training materials on new features and methodologies. - Stay current with and propose the internal use of industry approaches, algorithms, and practices. Communication Skills:: - Ability to communicate technical information in an organized and understandable fashion. - Customer oriented approach with a demonstrated concern and desire to work with and assist customers. - Good organizational skills with the ability to multitask, prioritize, and track many activities. - Outstanding oral and written communication skills. Interested,please drop your updated resume to

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    2 weeks ago

    Hyderabad, Telangana, India ACL Digital Full time ₹ 8,00,000 - ₹ 15,00,000 per year

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    7 days ago

    Hyderabad, India ACL Digital Full time

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    7 days ago

    Hyderabad, India ACL Digital Full time

    RTL FPGA Design Engineer Experience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates. Interested,please share your updated resume to

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    Hyderabad, India ACL Digital Full time

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    Hyderabad, India ACL Digital Full time

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    2 days ago

    hyderabad, India ACL Digital Full time

    RTL FPGA Design Engineer Experience : 2-4 years Location : Hyderabad FPGA architecture Vivado Flow Scripting and automation Verilog / VHDL HW debugging We are looking for some background of scripting and or conceptual understanding of Power for experienced candidates. Interested,please share your updated resume to janagaradha.n@acldigital.com