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RTL Design Engineer
4 months ago
•Exp level 5 to 8 years
Expertise and hands on experience in Verilog/RTL design for IP or SoC.
• Command and thorough knowledge on digital logic design concepts.
• Must have worked on at least one large IP block and have in depth knowledge of IP block design/architecture.
• Must have experience in Synopsys/Cadence/Mentor simulation tools and debugging skills.
• Desirable Perl/TCL scripting and automation knowledge
• Desirable experience in RTL logic synthesis, sdc and constraint writing experience
• Understanding of basic soc architecture std-cells, IO blocks etc.
