RTL Designer

Job Description: B.tech or M.tech with 5+ years of experience on FE tools like Spyglass cdc and spyglass lint. Should have sound knowledge on synthesis and low power. Should have good knowledge on RTL coding and integration with excellent debug skills. Knowledge on git and CC framework will be better.Role involves running FE tools on DSP designs...

Job Description: B.tech or M.tech with 5+ years of experience on FE tools like Spyglass cdc and spyglass lint. Should have sound knowledge on synthesis and low power. Should have good knowledge on RTL coding and integration with excellent debug skills. Knowledge on git and CC framework will be better.Role involves running FE tools on DSP designs...

Job Title: RTL Design EngineerLocation: Bengaluru, Karnataka, IndiaDuration: Full TimeJob description• 5+ years of experience in front end RTL design and front-end tools and flows• Experience in SOC integration, RTL release flows, clocking and reset architecture.• Experience in post RTL checks — Lint, CDC, RDC• Experience in RTL synthesis and...

Job Title – RTL Design EngineerJob Description –-Strong in Digital Design-Knowledge of VHDL/Verilog/System Verilog-Lint/CDC/Timing Closure-Knowledge of Validating IP, debugging of failures on target boards, board bring up.-Proficiency in Linux environment.-Good Communication skills.Basic job Deliverables – RTL Coding, IP Design, CDC, LINT, Vivado...

Experience Level : 1-2 Years Only• 1-2 Years experience in SoC/IP RTL Design• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.About the Group:The Sitara MPU product line is a rapidly expanding business within TI, investing to address the fast-growing segment of high-performance processors in industrial &...

Experience Level : 1-2 Years Only• 1-2 Years experience in SoC/IP RTL Design• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.About the Group:The Sitara MPU product line is a rapidly expanding business within TI, investing to address the fast-growing segment of high-performance processors in industrial &...

Company: Qualcomm India Private Limited Job Area: Engineering Group, Engineering Group > Hardware Engineering General Summary: As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for...

Job Description - Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)- Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and...

Job Description- Synthesis, Equivalence Checking, Clock-Domain Crossing (CDC) Analysis, Area/Power optimizations, Linting, Static Timing Analysis (STA)- Write design specifications for different functional blocks on a chip, Create micro-architecture diagrams of functional blocks, Design functional blocks using System Verilog RTL code, conduct Synthesis and...

Hi FolksGreetings from Tech Mahindra!!Role: RTL Lead EngineerExp: 8+ yearsLocation: Bangalore/ Kochi/ Vizag/ AhemdabadAbout JobArchitecture DevelopmentExperience in developing High Level Architecture for a Design Requirement from Specification levelExtract Micro Architecture from High Level Architecture specificationRTL Design - Coding & IntegrationDevelop...

•RTL Design Experience•Low Level HW & SW Security Experience & secure programming Experience Required 8 - 10 Years Industry Type IT Employment Type Permanent Location India Roles & Responsibilities Senior engineer Expertise & Qualification Btech

•RTL Design Experience•Low Level HW & SW Security Experience & secure programming Experience Required 8 - 10 Years Industry Type IT Employment Type Permanent Location India Roles & Responsibilities Senior engineer Expertise & Qualification Btech

RTL Design Engineers / Leads / Managers Experience: ~3 to 18+ YearsLocations: India, Hyd, Delhi (NCR), Chennai, Bangalore, Kerala, Ahmedabad, Pune, Mumbai, Etc).Job Description: Expertise in SoC/IP design.Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.In depth knowledge on RTL quality checks (Lint,...

RTL Design Engineers / Leads / Managers Experience: ~3 to 18+ YearsLocations: India, Hyd, Delhi (NCR), Chennai, Bangalore, Kerala, Ahmedabad, Pune, Mumbai, Etc).Job Description: Expertise in SoC/IP design.Expertise in IP design, Subsystem/Cluster and SoC level integration using Verilog/System Verilog.In depth knowledge on RTL quality checks (Lint,...

Hello Visionary! We know that the only way a business thrive is if our people are growing. That’s why we always put our people first. Our global, diverse team would be happy to support you and challenge you to grow in new ways. Who knows where our shared journey will take you?Siemens founded the new business unit Siemens Advanta (formerly known as...

Hello Visionary! We know that the only way a business thrive is if our people are growing. That’s why we always put our people first. Our global, diverse team would be happy to support you and challenge you to grow in new ways. Who knows where our shared journey will take you?Siemens founded the new business unit Siemens Advanta (formerly known as...

Job description:Junior Engineer – 3 to 5 Years ExpHe should work with lead and program Manager.Self-motivated person.minimum 3 years relevant expRTl Exp is must , not require to code need proficient knowledge.RTl, Lint & CDC, GIT mandatory.Mode of Interview ( F2F)

Position: RTL Design (Design /Sr. design Engineer/Design Lead /Sr. Design Lead/Manager/Sr. Managers)Experience: 3 years to 20 years relevant experience.Location - India and Onsite.Technical Skillset Required:RTL Design using VerilogSOC IP IntegrationInterconnect Protocols: AHB, AXI, APBSOC Interfaces: GPIO, SPI, I2C, UARTHigh Speed Serial Interfaces: PCIe...

DESIRED PROFILE : - Master's and/or Bachelor's degree in engineering (or equivalent) in EC/ EE/ CS with 3 or more years of experience in digital SoC development.- Experiences in RTL design using Verilog / SystemVerilog / VHDL for CPU / control sub-systems (AXI / AHB / APB bus), digital signal processing blocks(FIR filter, FFT/IFFT, NCO)-...

Job Location: BangaloreNotice Period: 15 days to 30 DaysMinimum: 5+ Years1.Experience in Low power RTL design, microarchitecture, synthesis, timing closure, Low power estimation. Should be proficient in Verilog.2. Should have experience in optimization of microarchitecture and RTL for area and power reduction. Experience with Arithmetic units, Floating point...