Physical Design Manager
3 weeks ago
Roles & Responsibilities
Job Description:Good exposure in handling block/SOC level RTL-gds2.Capable in handling block-level timing closure.Excellent knowledge on all low power & checks, like MVRC/CLP, LEC/Formality, DRC, LVS, IR, EM.Good scripting skills (TCL/SHELL/PERL).Experience on low power implementation techniques is preferred.Prior experience in lower tech nodes like 10nm, 7nm, 5nm is preferred.Synopsys/Cadence tool experience is preferred.Should be comfortable with methodologies and guidelines.Expertise in Floor Planning, Power Planning, CTS.Handling Client requirements and day to day activitiesRequired Qualification:Bachelor’s degree in Electronics & Communication/Electrical & Electronics. Master’s degree in VLSI is preferred.Experience 12+ years of relevant experienceProven ability to identify, assess and solve problemsAnalytical with good interpersonal skillsGood CommunicationExcellent team playerHigh IntegrityMentoring Team MembersPrior experience of leading a team of Engineers.
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