Senior Design Verification Engineer

4 weeks ago

Noida, India Cadence Design Systems Full time

Job Title: Principal Product Validation Engineer

Location: Noida

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success.
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests.
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Responsibilities & Skills: (Design Verification Engineer)

  • The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).
  • Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools.
  • Experience in process automation with scripting.
  • Experience with SystemVerilog, C++, UVM.
  • Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.
  • Experience designing and implementing complex functional verification environments is required.
  • Must have solid experience on any of the protocols like Ethernet, PCIe, DDR, USB3/4, DisplayPort(DP), MIPI, UCIe, NVMe, HDMI.

Qualifications

Minimal qualification requires BS/MS degree ECE or CS with 7+ years of experience in relevant experience.

Behavioral skills required.

  • Must possess strong written, verbal and presentation skills.
  • Ability to establish a close working relationship with both customer peers and management.
  • Explore what’s possible to get the job done, including creative use of unconventional solutions.
  • Work effectively across functions and geographies.
  • Push to raise the bar while always operating with integrity.

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