PCIe Design Verification Lead
4 weeks ago
Hope you're doing well
We are hiring for the PCIe Design Verification Lead role. Please find the JD below
JOB Designation: PCIe Design Verification Lead
JOB Location: PAN India
Mode of Hiring: Full time (FTE)
Notice Period: Immediate to 60 days
Experience:7+ years
Required Skills:
- 7+ years of experience in design verification, with a focus on PCIe protocol.
- Deep understanding of PCIe specifications and protocols, including PCIe Gen3/Gen4/Gen5.
- Proficiency in verification languages such as System Verilog and methodologies like UVM.
- Experience with industry-standard simulation tools and environments (e.g., Cadence Incisive, Synopsys VCS).
- Strong leadership skills with the ability to lead and mentor a team of verification engineers.
- Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams.
- Experience with scripting languages (e.g., Python, Perl) for automation is a plus.
- Familiarity with advanced verification techniques such as formal verification, assertion-based verification, and emulation is desirable.
If anyone is interested, please send an updated CV to
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