Manager - Design Verification

3 weeks ago

Bengaluru, India GreenWave™ Radios Full time

#GreenWave Radios is looking for a #DesignVerification (DV) Manager  to join a growing start up semiconductor development organization and to help drive excellence in our 5G ORAN products.

Key Responsibilities

  • Manage 10-12 DV & design engineers for technical leadership and mentoring team members for team building
  • Work as the primary interface to US design/verification team members and management
  • Track verification progress, Identify and close verification gaps to show progress towards tape-out.
  • Provide an executive summary for the verification status on each sub-system
  • Full-chip functional verification of 5G Digital Radio #SOC
  • Develop, review and execute SOC verification plans on internal and 3rd  party IPs
  • Architect verification framework for mix-signal SOC verification
  • Verify full chip SoC using #UVM - Directed/Constrained-Random 
  • Verify internal and 3rd  party IP blocks with functional vector, VIP and UVM
  • Collaborate with cross functional teams (System, Emulation, FW) for silicon tapeout and product solution development
  • Explore and propose advanced verification methodologies - UVM, FPGA prototyping, emulation,

Minimum Qualifications

  • Tech or B.Tech degree in Electrical or Computer Engineering or equivalent
  • 15+ yrs of successfully executing and/or managing multiple IP, SOC Verification projects
  • Have successfully led verification efforts at IP and/or SOC level for multiple
  • Extensive experience in developing UVM-based SV test-benches - Directed/Constrained-Random
  • Deep understanding and knowledge of verification methodologies, flows and quality
  • Prior work experience with complex coverage-driven random constraint UVM
  • Putting together complex UVM environments from scratch is a
  • Strong experience with digital logic design, and logic verification methodology
  • Hands-on experience with CNDS simulation and verification tools (Xcelium, vManager)
  • Hands-on experience in 3r party IP verification using VIPs from CNDS/SNPS with front/back-door loading/configuration
  • Hands-on experience in multi-core ARM CPUs & AXI/AHB/API bus system verification
  • Hands-on experience developing verification collateral in System Verilog and UVM
  • Familiar with Version control software like Git, Subversion
  • Familiar with gate-level simulation
  • Familiar with boot rom simulations
  • Familiar with matlab simulations
  • Experience on FPGA emulation
  • Good knowledge of programming languages such as C, VHDL, System-Verilog and scripting language like TCL and Python.

Preferred Skills

  • Knowledge of ARM and Wireless signal-processing design is highly
  • UVM Proficiency is required
  • Strong communication skills both written and
  • Ambitious and goal oriented
  • Collaborate effectively in a dynamic team environment.

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