Senior Design Verification Engineer
2 months ago
Job Description
Engineer would be responsible for ensuring that the design is in line with the technical and quality requirements set for the team – particularly with respect to functional and code coverage.
Responsibilities
Experience in multiprotocol PHY/ PHY verification is a must
Good experience in SV & UVM is a must
Good debugging skills is a must
Role: Individual contributor and a good team player
Desired Skills
SOC Verification.
UVM and System Verilog
Location: Bangalore, Hyderabad, Chennai
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