Layout Director
1 month ago
Layout Director
About Us
We are a technology consulting company delivering best-in class Chip Design Services.
Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.
With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills
Our embedded design services are centered around FW validation & Test Automation
Chip Design Services
Analog IP Design
Foundation - OpAmp, Bandgap
IOs - GPIO, I2C, LVDS
Clocking - PLL
Power - LDO
SoC Design
RTL Design, Integration, Lint/CDC/RDC, UPF
IP/SoC UVM Verification
PPA, Synthesis, Constraints Management
Physical Design, Timing Closure, ECOs
Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC
PDK, Design Automation
DRC/LVS/Extraction Rule deck Development
PCell Development
Automation Tools in Perl, Python, GoLang
Approach
We support a mix of engagement models to support diverse client requirements.
Engagement Models
Turnkey (SoW) Engagement
Staff Augmentation (T&M)
Offshore Design Center
Key Enablers
Hands on Leadership
Proven Industry Experts
TSMC DCA Parternship
Collaboration with Academia
Location: Hyderabad
Layout Director
### Job Description: Layout Director
#### **Job Summary:**
We are seeking an experienced and dynamic Layout Design Manager to lead our layout design team. The ideal candidate will have a strong background in analog-on-top chip layout for devices with high-speed IO and analog components, as well as experience in dealing with ESD/latch-up issues, bump matrix design, RDL routing, power distribution, and critical signal planning. This role requires excellent leadership skills, the ability to manage complex design projects, and a strong technical background in layout design.
#### **Key Responsibilities:**
- **Team Leadership:**
- Lead, mentor, and manage a team of layout design engineers.
- Foster a collaborative and innovative team environment.
- Develop team skills through training and professional development initiatives.
- **Project Management:**
- Plan and estimate layout design tasks, resources, and schedules.
- Track and report on project progress, ensuring timely delivery of milestones.
- Coordinate with cross-functional teams, including design, verification, and packaging, to align layout design activities with project goals.
- **Analog-on-Top Layout Design:**
- Oversee the layout design of analog-on-top chips with high-speed IO and analog components.
- Ensure designs meet performance, power, area, and manufacturability requirements.
- Optimize layout for ESD and latch-up prevention, signal integrity, and noise immunity.
- **Bump Matrix and RDL Routing:**
- Manage the design of bump matrix and redistribution layer (RDL) routing for advanced packaging.
- Ensure efficient power distribution and critical signal planning.
- **ESD/Latch-Up and Power Distribution:**
- Address and resolve ESD and latch-up issues in layout designs.
- Design robust power distribution networks to ensure reliable chip operation.
- **Critical Signal Planning:**
- Plan and implement critical signal routing to minimize interference and maximize performance.
- Optimize layout for signal integrity and timing closure.
- **Hiring and Training:**
- Participate in the hiring process to recruit top talent for the layout design team.
- Provide training and mentorship to new hires and junior engineers.
- **Continuous Improvement:**
- Stay updated with the latest industry trends, tools, and methodologies in layout design.
- Drive continuous improvement initiatives to enhance design processes and methodologies.
- Implement best practices for layout design and contribute to the development of standards and processes.
#### **Qualifications:**
- **Education:**
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- **Experience:**
- 15+ years of experience in layout design, with at least 3 years in a managerial or leadership role.
- Proven experience in analog-on-top chip layout for high-speed IO and analog devices.
- **Technical Skills:**
- Extensive experience with ESD and latch-up prevention techniques.
- Proficiency in bump matrix design and RDL routing.
- Strong knowledge of power distribution networks and critical signal planning.
- Familiarity with CAD tools (e.g., Cadence Virtuoso, Mentor Graphics) for layout design.
- Experience with physical verification (DRC, LVS) and parasitic extraction.
- **Soft Skills:**
- Excellent leadership and team management abilities.
- Strong problem-solving and analytical skills.
- Effective communication and interpersonal skills.
- Ability to work in a fast-paced, dynamic environment and manage multiple projects simultaneously.
#### **Preferred Qualifications:**
- Experience with advanced node technologies (e.g., FinFET, SOI).
- Knowledge of reliability testing and failure analysis for analog and high-speed IO circuits.
- Familiarity with scripting languages (e.g., Python, Perl) for automation.
Contact:
Uday
Mulya Technologies
"Mining The Knowledge Community"
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