Design Verification Engineer – Fabric/On Chip Network Verification
4 weeks ago
Design Verification Engineer – Fabric/On Chip Network Verification
Design Verification Engineer – Fabric/On Chip Network Verification
Your Role and ResponsibilitiesAs a Functional verification engineer, you will be working on the latest generation of high end, state-of-the-art micro-processors used in
servers.Lead the development of the verification plans, environment, testbenches and writing testcases for the Cache Coherency Transport Interconnect Fabric in Server Processors.Develop skills in Functional verification tools and methodologies.Work with design as well as other key stakeholders in debugging and fixing logic design issues and deliver a quality designWork with development team to ensure coverage criteria is met.Posting Country
India
State / Province
Karnātaka
City / Township / Village
Bangalore
Travel Required
No Travel
Position Type
Professional
Required Education
Bachelor's Degree
Required Technical and Professional Expertise9+ years of experience in Functional Verification of processors or ASICs.3+ years of experience in the following areasComputer architecture knowledge.Multi-processor Cache Coherency Transport/Network on Chip/Memory Hierarchy verification.AXI/AHB/ACE/ACE-lite/CHI/On Chip System Fabric interface verification or any other Processor/SoC coherency transport interconnect fabric verification.Knowledge of performance parameters of On Chip Coherency Transport Network designs and ways to stress verify themMinimum one full life cycle leadership experience of a processor/SoC verification flow with focus on Coherency Transport Interconnect and/or Network on Chip VerificationGood object-oriented programming skills in C++/SystermVerilog, scripting languages like Python/Perl.Verification knowledge in Clock domain crossing and reset domain crossingKnowledge of functional verification methodology like UVM/OVMKnowledge of HDLs (VHDL/Verilog)Developed test plans and test strategies for IP/unit/block level verification of Coherency Transport InterconnectsDevelopment experience on Linux/Unix environments, GIT repositories and good understanding of Continuous Integration and DevOps workflowExposure in developing testbench environment, write complex test scenario, debugging and triaging failsExperience in driving verification coverage closure including performance testing, stress testing and ability to identify corner case scenarios.Preferred Technical and Professional ExperienceGood understanding of computer system architecture and microarchitecture.Knowledge of design patterns in programmingPreferred Education
Master's DegreeContact:UdayMulya Technologies"Mining The Knowledge Community"
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