Senior Design Verification Engineer

4 weeks ago


Delhi, India Analog Devices Full time
Job Description:The Engineering Enablement team is responsible for providing industry leading tools, methodologies, and support to engineering teams to accelerate product development across the company. This position is for an opening in the “Systems Verification and Validation team” within the Engineering Enablement organization in the CTO Office. This team works to define and promote the adoption of verification best practices, including Metric-driven verification, UVM, Formal, FuSA, Security, Portable Stimulus, Emulation and FPGA prototyping technologies. This role is focused on leading and supporting product lines on ADI proprietary and industry standard “Digital Systems Verification and Infrastructure” flows and deployment of industry-leading verification tools, best practices, and methodologies across business units at ADI.Job Responsibilities:3rd party, industry-standard simulator productivity improvements and breakthrough innovations, integration into ADI DV solutions and creating differentiating solutionsEvaluate, utilize existing and develop new verification infrastructure frameworks, tools, and methodologies to enhance the verification process for efficiency and qualityConsulting design teams on verification best practices and approaches and providing the right solutionsTraining, deployment, and support of verification methodologies within ADIEngaging with EDA vendors to influence their development roadmaps to meet ADI’s requirements into the futureJob Requirements:BTech/MTech degree in Electrical/Electronics/VLSI with 5-8 years of experience from reputed institutesStrong hands-on experience in Cadence/Synopsys simulation and debug tools like Xcelium/VCS, vManager, Verisium, Verdi or similar is requiredExpertise in automation and scripting languages like Perl, Python, and shell scriptingExpert knowledge in DV methodologies like GLS, Coverage, MSIE (Multi snapshot incremental elaboration)Prior experiences in Low Power Verification is highly preferredProficient in Version control systems, such as Perforce, SVN, SOSProficient in Verilog, System Verilog and UVMAbility to manage multiple tasks and work effectively in a fast-paced environmentAble to communicate effectivelyGood debugging and analytical skills.



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