Senior Design Verification Engineer- Singapore
1 week ago
Over 4 years of experience in digital IP verification, with advanced knowledge of ASIC/SOC design flow and modern verification methodologies. About the Role Proficient in Verilog, SystemVerilog, and UVM. Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard). Responsibilities Skilled in defining and developing UVM-based verification frameworks, testbenches, processes, and flows. Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet (plus). Knowledge of AMBA interconnects (AXI, APB, AHB) (plus). Qualifications Over 4 years of experience in digital IP /SOC verification. Required Skills Advanced knowledge of ASIC/SOC design flow. Proficient in Verilog, SystemVerilog, and UVM. Strong understanding of UVM concepts and SystemVerilog features (SVA, UVM Scoreboard). Preferred Skills Exposure to high-speed protocols such as USB, PCIe, UFS, SATA, Ethernet. Knowledge of AMBA interconnects (AXI, APB, AHB).
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Hyderabad, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...
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hyderabad, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: Test bench development and debug Strong Expertise in Digital, Verilog & SV. UVM/C based test case development and debug. Power aware test case development and debug External/Internal VIP based test development and debug. Mixed-signal block modelling and RNM based...
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Senior Design Verification Engineer SIngapore
2 weeks ago
Hyderabad, India BITSILICA Full timeJob Description Skill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal...
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Senior Design Verification Engineer SIngapore
2 weeks ago
Hyderabad, Telangana, India, Telangana BITSILICA Full timeSkill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 days JD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV Engineer Exp: 5-10 Years Location: Singapore Notice: Immediate - 30 days JD: - Test bench development and debug - Strong Expertise in Digital, Verilog & SV. - UVM/C based test case development and debug. - Power aware test case development and debug - External/Internal VIP based test development and debug. - Mixed-signal block modelling and...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 daysJD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...
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Hyderabad, India BITSILICA Full timeSkill: Senior DV EngineerExp: 5-10 YearsLocation: SingaporeNotice: Immediate - 30 days JD:Test bench development and debugStrong Expertise in Digital, Verilog & SV.UVM/C based test case development and debug.Power aware test case development and debugExternal/Internal VIP based test development and debug.Mixed-signal block modelling and RNM based...
