RTL IP design Engineer
3 weeks ago
Job Title:RTL IPdesign Engineer
Experience:3-10 Years
NoticePeriod: Immediate to 15 days
Location: Hyderabad
JD:
KEYRESPONSIBILITIES:
·Understand RTL at structural level,IP boundaries, IP parameters.
·Understand IP design.
·Add assertions where needed.
·Generate various constraintsnecessary for the build flow setup and maintenance.
·Do the quality checks of the IP likeLint/CDC/RDC/Synth/Timing checks/waiver creation across milestones.
·Participate in IP integration to thesubsystem level.
·Write sample test bench to verifythe basic functionality of the IP/block.
·Do the first level of triage of thefunctional issues reported.
·Understand the reports out ofquality checks such as Lint/CDC/RDC/Synth/Timing checks and suggest fix in theRTL
·Work with functional verificationteam to meet coverage and quality standards.
·Guarantee quality/timelydeliverables meeting projects’ schedule.
·Help to improve/automate designprocess.
PREFERREDEXPERIENCE:
·Knowledge of ASIC development flows
·Knowledge of front-end RTL designtools and methodologies.
·Knowledge of systemverilogMulti-clock domain designs.
·Design constraints for synthesis andstatic timing analysis.
·Experience in rtl linting tools,reset domain crossings, clock domain crossings, synthesis, RAM generation(area, timing, power)
Knowledge of AXI/AMBA protocol
·Knowledge of front-end requirementsand deliverables for verification, validation, physical design, architecture,security, dfx, power.
·Verification - coverage, test plan,debug
·Physical design timing, clockcrossings, reset crossings, ECOs (manual, formal)
·Ability to work and effectivelycollaborate with partners
·Knowledge of scripting languageslike Perl, tcl or cshell
·Experience with DMAs, PCIe, ordering,datapath virtualization, performance, flow control a plus.
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