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Soc Power Architecture

4 weeks ago

Hyderabad, India Advanced Micro Devices, Inc Full time
WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. AMD together we advance_ The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.The Role: We are looking for an experienced engineer to join the SOC Power Modeling team in the AMD Client Computing and Graphics group. This role involves collaboration with multiple engineering teams including SoC architecture definition, IP design, integration/physical design, verification, and platform architecture. Contributions have a direct impact on the power & performance of AMD’s Client products. The Person: The candidate should have SOC design process experience from front end to tapeout. The candidate will work closely with the SOC design teams on RTL and emulation-based power estimation, simulation and design data extraction. The candidate must be organized, self-motivated and able to work effectively on teams large and small across multiple sites. He or she must be able to prioritize assignments and drive them to completion. Good verbal and written communication skills are helpful for technical discussions with team members across the globe. Key Responsibilities: Work with front end RTL, DFT, Synthesis, and Physical design teams in the development of power intent (UPF) design at SoC level. Work with emulation team on power estimates during the pre-silicon design process using Power Artist/PTPX emulation environments and ensure power objectives and goals are met. Work with RTL and physical design teams to generate data on design impact from clock and power gating, device type mix and physical implementation options. Track IP power development through the design cycle ensuring it meets power budgets - leakage/dynamic at every milestone. Work with design verification in validating low power design features at SoC and IP level. Preferred Experience Experience with Synopsys EDA tools, particularly PtPx/Power Artist. Understanding of hardware emulation process, stimulus and EDA flows. Experience with Tcl and Python based scripting. Experience with UPF. Academic Credentials Master or Bachelor of Science degree in Electrical Engineering. 3+ years of experience. #LI-RR1 #LI-Hybrid
Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.