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Analog Layout Engineer
3 months ago
www.Sevyamultimedia.com
Analog Layout Engineer
About Us
We are a technology consulting company delivering best-in class Chip Design Services.
Founded in 2008, we partner with top semiconductor companies in building a connected, safer tomorrow.
With over 40+ tapeouts and expertise spanning the breadth of chip design, we offer a wide variety of Semiconductor skills
Our embedded design services are centered around FW validation & Test Automation
Chip Design Services
Analog IP Design
Foundation - OpAmp, Bandgap
IOs - GPIO, I2C, LVDS
Clocking - PLL
Power - LDO
SoC Design
RTL Design, Integration, Lint/CDC/RDC, UPF
IP/SoC UVM Verification
PPA, Synthesis, Constraints Management
Physical Design, Timing Closure, ECOs
Sign-off - Timing, Power, EM/IR, DRC/LVS/ERC
PDK, Design Automation
DRC/LVS/Extraction Rule deck Development
PCell Development
Automation Tools in Perl, Python, GoLang
Approach
We support a mix of engagement models to support diverse client requirements.
Engagement Models
Turnkey (SoW) Engagement
Staff Augmentation (T&M)
Offshore Design Center
Key Enablers
Hands on Leadership
Proven Industry Experts
TSMC DCA Parternship
Collaboration with Academia
Location: Hyderabad
Analog Layout Engineer
### Job Description: Analog/IO Layout Engineer (3-5 Years of Experience)
#### **Job Summary:**
We are seeking a talented and experienced Analog/IO Layout Engineer with 3-5 years of experience to join our engineering team. The ideal candidate will be responsible for creating high-quality analog and IO layout designs, ensuring compliance with design rules, and collaborating closely with circuit designers to achieve optimal performance and manufacturability.
#### **Key Responsibilities:**
- **Layout Design:**
- Design and implement layout for analog and IO circuits, including amplifiers, converters, regulators, PLL, bandgap and IO pads.
- Ensure layouts meet performance, power, area, and reliability requirements.
- Optimize layout for matching, noise immunity, and signal integrity.
- **Collaboration:**
- Work closely with circuit design engineers to understand design specifications and requirements.
- Collaborate with process engineers to optimize layout for manufacturability and yield.
- Participate in design reviews and provide feedback to enhance design quality.
- **Verification and Validation:**
- Perform layout versus schematic (LVS) and design rule checking (DRC) to ensure accuracy and compliance with design rules.
- Conduct parasitic extraction and analysis to validate layout performance.
- Address and resolve any issues identified during verification and validation.
- **Documentation and Reporting:**
- Create detailed documentation for layout designs, including design specifications, verification reports, and process guidelines.
- Present findings and recommendations to stakeholders.
- **Continuous Improvement:**
- Stay updated with the latest industry trends, tools, and methodologies in analog and IO layout design.
- Participate in continuous improvement initiatives to enhance design processes and methodologies.
#### **Qualifications:**
- **Education:**
- Bachelor’s degree in Electrical Engineering, Semiconductor Physics, or a related field. A master’s degree is a plus.
- **Experience:**
- 3-5 years of experience in analog and IO layout design or a similar role.
- **Technical Skills:**
- Proficiency in CAD tools (e.g., Cadence Virtuoso, Mentor Graphics) for layout design.
- Strong understanding of analog and mixed-signal circuit design principles.
- Experience with LVS, DRC, and parasitic extraction tools and methodologies.
- Knowledge of semiconductor fabrication processes and design rules.
- **Soft Skills:**
- Excellent problem-solving skills and attention to detail.
- Strong communication and teamwork abilities.
- Ability to work independently and manage multiple projects simultaneously.
#### **Preferred Qualifications:**
- Experience with advanced node technologies (e.g., FinFET, SOI).
- Familiarity with ESD and latch-up prevention techniques.
- Knowledge of reliability testing and failure analysis for analog and IO circuits.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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