STA Lead

KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR STA and timely feedbacks to PD team Generating block level HS session and using Top...

KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR STA and timely feedbacks to PD team Generating block level HS session and using Top...

Skills RequiredNetlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and...

Job Description Back Lead Static Timing Analysis (STA) Engineer - Bangalore, India - 10+ - Full-Time We are seeking an experienced Lead STA Engineer to take ownership of the static timing closure process for complex ASIC/SoC designs. In this role, you will lead timing sign-off activities, coordinate with cross-functional teams, and ensure designs meet...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

Hello All,Eximietas Design Hiring STA Engineers/LeadsExperience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Experience in Static Timing Analysis (STA) for ASIC designs.Experience in developing timing constraints.Experience in timing closure and...

Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you’ll lead timing closure efforts across block and full-chip levels,...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

Job Description Company Description Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable todays needs and tomorrows next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world...

Job Description Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. Job Description - In your new role you will: - Implement high-performance, low-power, and area-efficient digital designs. - Write and implement block level and top-level constraints for Synthesis, Static Timing Analysis. - Optimize designs for...