STA Lead

KEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnR STA and timely feedbacks to PD team Generating block level HS session and using Top...

Skills RequiredNetlist and constraint sign in checks and validation.Prime time constraint development at full chip level and clean up.Multimode multi corner timing knowledge and timing closure at sub HM/block/top level.Top level timing closure with sign off STA in MMMC with Xtalk and OCV. Top level ECO implementation strategy development for netlist, RTL and...

Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to...

Job Description WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiencesfrom AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to...

Technical Skills:Well versed with the timing closure (STA), timing closure methodologies.Pre/Post-layout constraint development to timing closure.Handshake with the design team and develop functional/DFT constraints.IP level constraint integration.Multi-voltage/Switching aware corner definitions.RC/C model selection understanding.Abstraction expertise like...

Hello All,Eximietas Design Hiring STA Engineers/LeadsExperience: 10+ Years.Location: Bengaluru or Visakhapatnam or San Jose, Bay Area, & Austin, USA.Anyone with a Valid H1B or Already in US.Job Description:Experience in Static Timing Analysis (STA) for ASIC designs.Experience in developing timing constraints.Experience in timing closure and...

Tenstorrent is looking for a skilled and detail-oriented Static Timing Analysis (STA) Engineer to help us deliver first-pass silicon success for our cutting-edge AI and RISC-V SoCs. Engineers with a strong foundation in Static Timing Analysis (STA) and timing constraints . In this role, you’ll lead timing closure efforts across block and full-chip levels,...

BE /BtechEXp- 5- 12 YrsWork on challenging DDR PHY IP & Testchip Physical Design from Netlist-to-GDS in tech nodes below 7nm.• Take ownership of one or more physical design blocks includes all of, floorplan, CTS, PNR, QRC, STA, PV & IR.• Contribute to design methodology, flow automation.• Innovate & implement Power, Performance and Area optimization...

Job Title: STA Engineer – VLSI Location: Bangalore Company: Tessolve Experience Required: 4+ years Educational Qualifications: Bachelor's or Master’s degree Job Description:We are seeking a skilled Static Timing Analysis (STA) Engineer with experience in the VLSI domain. The ideal candidate will be responsible for performing and analyzing timing across...

Job Title: STA Engineer – VLSI Location: Bangalore Company: Tessolve Experience Required: 4+ years Educational Qualifications: Bachelor's or Master’s degree in Electrical/Electronics Engineering, VLSI, or related fields Job Description:We are seeking a skilled Static Timing Analysis (STA) Engineer with experience in the VLSI domain. The ideal candidate...