Physical Design Engineer
2 weeks ago
Job Title: Physical Design Engineer – DDR/HBM/UCIe IP Implementation
Location: Hyderabad
Experience: 4-7 Years
Job Description:
We are looking for a Physical Design Engineer with strong technical fundamentals and hands-on expertise in timing closure (2GHz+), mixed-signal hard macro integration, and clock tree optimization. The role involves daily collaboration with local and US counterparts, focusing on the implementation and integration of Die-to-Die (D2D) IPs at advanced technology nodes (14nm, 10nm, 7nm, 5nm, and below).
Key Responsibilities:
- Implement and integrate DDR, HBM, and UCIe IPs at advanced nodes.
- Drive timing closure, skew balancing, and mixed-signal hard macro integration.
- Optimize clock tree synthesis with tight skew requirements.
- Collaborate with global teams to resolve technical challenges.
- Mentor junior engineers within the team.
Technical Skills:
- Strong expertise in SNPS tools: DC, PT, PT-SI, ICC2.
- Prior experience in DDR, HBM, UCIe implementation is a plus.
- Solid understanding of timing closure, CTS, and physical design methodologies.
Preferred Qualifications:
- Bachelor's/Master's degree from a reputed university.
- Strong problem-solving skills and ability to work in a collaborative environment.
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