Senior ASIC RTL Design

2 weeks ago


Chennai Metropolitan Area, India Mulya Technologies Full time
  • Name of position: Senior ASIC RTL Design
  • Number of Positions: 2
  • Location of Position: Hyderabad/Bangalore/Chennai
  • Mode of work: In office [5 Days] [For Bangalore/Chennai it will be remote]
  • Required Experience level: 8+ years
  • Required Key Skills: RTL Logic Design, Interface Protocols [PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.]
  • Required Qualifications: BTech/MTech


Note:

  • Hyderabad will be the first priority as location.
  • For Bangalore/Chennai it will be remote as they have office in Hyderabad

Company Description

We are a AI-enhanced security processor company redefining the control and management of every digital system. The company was founded in 2017 and currently has 100+ employees. developing great technology takes more than talent: amazing people who understand collaboration, respect each other and go the extra mile to achieve exceptional results. It takes people who have the passion and desire to disrupt the status quo, deliver innovation, and change the world. We invite you to apply for this job if you have this passion.


Job Description


ASIC/SoC Design position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT. You should have prior knowledge of logic design and computer architecture. As the ASIC/SoC Design Engineer , you will have the opportunity to work in all areas of the SoC design flow. You will work closely with the Architecture, Verification, Physical Design and Software teams, and report to the Director of Engineering.


KEY RESPONSIBILITIES


  • Help develop the design and implementation of SoCs.
  • Micro-architecture design, RTL coding, synthesis, timing closure, and documentation of various RTL blocks;
  • Top-level and block-level performance, bandwidth, and power optimization;
  • Work with FPGA engineers to perform early prototyping; and
  • Support test program development, chip validation, and chip life until production maturity.
  • Collaboration with firmware, software, DV, FPGA, DFT, SoC integration, and backend teams throughout various stages of ASIC development.

Qualifications

  • 8+ years of experience in RTL logic design, verification, synthesis, and timing optimization;
  • Proficient in writing clear, implementable micro-architecture specifications;
  • Expertise in writing efficient RTL code in Verilog and SoC integration
  • Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure;
  • Should have worked on interface protocols like PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
  • Experience in design bringing up and debugging on FPGA-based emulation platforms like HAPS, and Veloce.
  • Fluency with scripting languages (e.g., Perl, Python);
  • Must have gone through at least one tape out.
  • Preferred: Silicon bring-up and debug experience
  • Experience in working with repository management tools like Bitbucket/ Jenkins and bug-tracking tools like JIRA.

Additional Information

We are committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology, and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence, and high curiosity over pedigree alone. Working hard and smart, continuous learning, and mutual support are all part of who we are.



Contact:

Uday

Mulya Technologies

muday_bhaskar@yahoo.com

"Mining The Knowledge Community"



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