ACL Digital
4 weeks ago
Senior Network Software Developer - L2/L3 IP Multicast to join our dynamic team in Bengaluru.Job Summary :We are seeking a highly skilled and experienced Senior Software Engineer with a strong background in L2/L3 multicast development to join our dynamic team. The ideal candidate will possess in-depth knowledge of multicast protocols and network topologies, coupled with excellent programming and problem-solving abilities. You will be responsible for designing, developing, and implementing advanced multicast networking :- Design, develop, and implement features and enhancements related to L2/L3 multicast protocols.- Work extensively with IGMPv2/v3 and PIM (Protocol Independent Multicast) in various modes (e.g., Dense Mode, Sparse Mode, Source-Specific Multicast).- Analyze and troubleshoot complex multicast networking issues.- Contribute to the architecture and design of multicast network solutions.- Develop and maintain high-quality code in C, C++, and/or Python.- Collaborate effectively with cross-functional teams, including QA and hardware engineers.- Participate in code reviews and ensure adherence to coding standards.- Stay up-to-date with the latest advancements in networking technologies and multicast protocols.- Contribute to the development of technical documentation.Required Skills and Experience :- Bachelor's or Master's degree in Computer Science, Electrical Engineering, or a related field.- 6+ years of experience in software 1 development with a strong focus on networking.- Proven experience in L2/L3 multicast development.- Deep understanding and hands-on experience with IGMPv2/v3 protocols.- Comprehensive knowledge of PIM (SM, DM, SSM) and its implementation.- Solid understanding of multicast network topology, including the roles and functionalities of Designated Router (DR) and Non-DR.- Excellent programming skills in C, C++, and proficiency in Python for scripting and automation.- Strong analytical and problem-solving skills with the ability to debug complex networking issues.- Experience with network simulation and testing tools.- Excellent communication and collaboration skills.Preferred Skills :- Experience with specific network operating systems (e.g., Cisco IOS, Juniper Junos).- Familiarity with other networking protocols (e.g., TCP/IP, VLAN, QoS).- Experience with network management systems.- Contributions to open-source networking projects. (ref:hirist.tech)
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Bengaluru, India ACL Digital Full timeHi All, ACL Digital is looking for "Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: - Must have good knowledge on the verification flows - Excellent hands-on debug skills and problem solving attitude. - Experience of working in complex test-bench/model in...
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Bengaluru, India ACL Digital Full timeHi All, ACL Digital is looking for "Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog,...
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Bengaluru, India ACL Digital Full timeHi All, ACL Digital is looking for "Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog,...
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Bengaluru, India ACL Digital Full timeHi All, ACL Digital is looking for "Senior Design Verification Engineers" Exp Level: 4+ years Notice period: Immediate to 30 days Location: Bangalore and Hyderabad Job Description: Must have good knowledge on the verification flows Excellent hands-on debug skills and problem solving attitude. Experience of working in complex test-bench/model in Verilog,...
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Senior Design Verification Engineers
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Bengaluru, India ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...
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Bengaluru, India ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...
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Senior Design Verification Engineers
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Bengaluru, India ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...
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Senior Design Verification Engineer
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Bengaluru, India ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...
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Senior design verification engineers
3 weeks ago
Bengaluru, India ACL Digital Full timeHi All,ACL Digital is looking for "Senior Design Verification Engineers"Exp Level: 4+ yearsNotice period: Immediate to 30 daysLocation: Bangalore and HyderabadJob Description:Must have good knowledge on the verification flowsExcellent hands-on debug skills and problem solving attitude.Experience of working in complex test-bench/model in Verilog, System...
