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CPU Micro-architect and RTL Design
4 months ago
CPU Micro-architect and RTL Design
Location: Bangalore
More about us:
We are a well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original RISC architecture, our processors have shipped into billions of consumer and enterprise products.
- Today, we are again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, we can accelerate development and deployment of RISC-V based solutions.
- CPU Micro-architect and RTL Design
- Location; Bangalore
CPU Micro-architect and RTL Design
Seeking experienced Micro-architect and RTL engineers to own and lead RTL development of one or more modules of a high-performance CPU core. Working knowledge of the pipeline stages of an in-order or out-of-order high performance CPU core is necessary. Candidate will be responsible for all aspects of the design including Performance, Power, and Area.
Minimum Qualifications
- MS degree in Electrical or Computer Engineering with BS degree with 9-13+ years of practical experience
- Through knowledge of microprocessor architecture including expertise in one or more of the following areas:
- Instruction fetch and decode, branch prediction
- Instruction scheduling and register renaming
- Out-of-order execution
- Integer and Floating-point execution
- Load/Store execution, prefetching
- Cache and memory subsystems
- Knowledge of Verilog and/or VHDL.
- Experience with simulators and waveform debugging tools
- Knowledge of logic design principles along with timing and power implications
Preferred Qualifications
- Experience with designing RISC-V, ARM and/or MIPS CPU
- Experience with Hardware multi-threading, virtualization, and SIMD designs
- Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
- Understanding of low power microarchitecture techniques
- Experience using a scripting language such as Perl or Python
Roles and Responsibilities
- Drive the micro-architecture and design of a critical CPU block or multiple blocks of a CPU core Performance exploration - explore high performance strategies working with the CPU modeling team.
- Microarchitecture development and specification - From early high-level architectural exploration, through micro architectural research and arriving at detailed specification.
- RTL ownership - Configurable Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
- Functional verification support - help the design verification team execute the functional verification strategy.
- Performance verification support - help verify that the RTL design meets the performance goals.
- Design delivery - work with multi-functional engineering team to implement and validate physical design on the aspects of timing, area, reliability, testability, and power.
More about us:
We are a well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original RISC architecture, our processors have shipped into billions of consumer and enterprise products.
Today, we are again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, we can accelerate development and deployment of RISC-V based solutions.
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
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