Senior Design Verification Engineer

Found in: Talent IN 2A C2 - 3 weeks ago


Hyderabad, India Cyient Full time

Hi,

Cyient is hiring for DV Lead.

Location : Hyderabad, Bangalore


Job Description

  • Looking for an experienced senior verification engineer with > 10 years of experience in ASIC/SOC/IP/block level functional verification using system verilog/UVM.
  • The ideal candidate will have strong command of UVM, advanced UVM and system verilog

Key responsibilities:

  • Develop a comprehensive test plan, complete test-bench and robust verification environment including interface agents and scoreboard in UVM
  • possess deep knowledge of at least one industry-standard protocol such as Ethernet, PCIe, DDR, USB
  • Strong debugging skills to address TB issues quickly and test failures.
  • Take responsibility for verification closure by addressing coverage and managing bug reports
  • proficiency in using industry standard verification tools such as Questa, VCS or ModelSim
  • Experience with scripting languages like python, perl or TCL for automation tasks
  • Manage a team of 6 to 7 Engg, Interact with the customer on the tasks and status updates


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