Senior STA Engineer
5 days ago
Job Title: Senior STA Engineer (Static Timing Analysis)Location: HyderabadExperience: 5+ yearsAt Best Nanotech, we are pushing the boundaries of Moore’s Law. Our silicon powers the world's most advanced [Product Type, e.g., Data Centers/Smartphones]. Our Physical Design team is looking for a timing expert to own the sign-off convergence for our latest SoC.The Role As an STA Engineer, you will be the gatekeeper of performance. You will be responsible for full-chip and block-level timing analysis and closure. You will work closely with the PD and RTL design teams to debug complex timing paths and drive the design to tape-out.Key Responsibilities- Sign-off Ownership: Perform Static Timing Analysis (STA) from netlist to tape-out using industry-standard tools. - Constraint Management: Develop and validate SDC (Synopsys Design Constraints) for complex multi-mode multi-corner (MMMC) designs. - Timing Closure: Analyze and fix Setup, Hold, Transition, and Pulse Width violations. - Signal Integrity: Analyze crosstalk (SI), noise, and OCV (On-Chip Variation) effects at advanced nodes (7nm and below). - ECO Implementation: Generate and implement functional and timing ECOs to fix critical paths. - Automation: Write Tcl/Python scripts to automate flows and improve analysis efficiency.What We Need (Requirements)- Education: B.Tech/M.Tech in Electronics, Electrical Engineering, or VLSI. - Tool Proficiency: Strong hands-on experience with Synopsys PrimeTime (preferred) or Cadence Tempus. - Tech Nodes: Experience working on deep sub-micron technology nodes (16nm, 7nm, 5nm). - Technical Depth: Solid understanding of digital logic, CMOS circuit design, standard cell libraries, and latch-based designs. - Scripting: Proficiency in Tcl, Perl, or Python for data parsing and flow automation.Nice to Have- Experience with Power Analysis (Voltage Drop / IR Drop) using RedHawk or Voltus. - Knowledge of hierarchical timing budgeting and low-power design techniques (UPF/CPF).Ready to Join? Click Apply Now to start the conversation or email talent@bestnanotech.in
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Senior Lead STA Engineer
1 day ago
New Delhi, India Connectpro Management Consultants Private Limited Full time#DSP_Senior_Lead_STA_Engineer_Noida.General Summary: As a Senior Lead STA Engineer, you will play a critical role in the design, optimization, verification, and timing closure of advanced hardware platforms. You will collaborate closely with cross-functional teams across design, physical implementation, and verification to ensure best-in-class performance,...
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STA Engineer
2 weeks ago
New Delhi, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | BangaloreWe are looking for skilled STA / PTPX Engineers with strong experience in timing sign-off and power analysis.️ Key Skills:• STA sign-off, MCMM timing closure• PrimeTime / PrimeTime-SI / PrimeTime-PX• PTPX power analysis (dynamic & static)• Timing constraints, ECOs,...
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STA Engineer
4 weeks ago
New Delhi, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilledSTA / PTPX Engineerswith strong experience in timing sign-off and power analysis. ️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints, ECOs,...
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STA Engineer
2 weeks ago
New Delhi, India Mirafra Technologies Full timeSTA Engineer | Noida, Bangalore (3-10 Yrs) & PTPX Engineer (10 Years) | Bangalore We are looking for skilledSTA / PTPX Engineerswith strong experience in timing sign-off and power analysis. ️ Key Skills: • STA sign-off, MCMM timing closure • PrimeTime / PrimeTime-SI / PrimeTime-PX • PTPX power analysis (dynamic & static) • Timing constraints, ECOs,...
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STA Engineers
4 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timeStatic Timing Analysis (STA) Engineer Job SummaryThe Static Timing Analysis (STA) Engineer will own the timing sign-off and closure for complex integrated circuits (ICs) and/or System-on-Chips (SoCs). This role involves defining and validating timing constraints, performing multi-mode multi-corner (MMMC) timing analysis, and collaborating with design and...
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STA Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeLooking for Senior STA Engineer.Exp.-7+yrs.Job Location- Bangalore/Hyderabad.Notice Period- Prefer Immediate joiner or less notice period.- Netlist and constraint sign in checks and validation. - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks - Prime time constraint generation/development at Top level,...
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STA Engineer
2 weeks ago
New Delhi, India ACL Digital Full timeLooking for Senior STA Engineer.Exp.-7+yrs.Job Location- Bangalore/Hyderabad.Notice Period- Prefer Immediate joiner or less notice period.- Netlist and constraint sign in checks and validation. - Experience with sign-off Static Timing Analysis, Logic equivalency checks, and Static Low Power Checks - Prime time constraint generation/development at Top level,...
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Sta Engineer
2 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timeJob Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilledStatic Timing Analysis (STA) Engineerto join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical...
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STA Engineer
2 weeks ago
New Delhi, India LeadSoc Technologies Pvt Ltd Full timeJob Title: Static Timing Analysis (STA) Engineer Job Overview We are looking for a highly skilledStatic Timing Analysis (STA) Engineerto join our ASIC/SoC design team. The ideal candidate will be responsible for performing timing analysis, developing constraints, and driving timing closure across multiple design stages. This role requires strong technical...
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STA Engineer
2 weeks ago
New Delhi, India MediaTek Full timeSTA EngineerKEY RESPONSIBILITIES: Responsible for Multi Voltage domain STA environment setup, execution and timing closure of GPU Drive the pre-route timing checks and QoR clean up to eliminate SDC issues and ensure a quality handoff for STA checks Ensuring timing correlation between PnRSTA and timely feedbacks to PD team Generating block level HS session...
