RTL Release Principal Design Engineer

2 weeks ago


Bengaluru, Karnataka, India Cadence System Design and Analysis Full time

Job Requirements

We are seeking a highly skilled Electronics or Computer Engineering professional with 7-10 years of experience.

The ideal candidate will have a strong background in the following areas:

  • RTL design flow steps, including RTL coding, simulation, compilation/testbench validation, synthesis, timing, DFT, lint, CDC, and LEC.
  • Debugging existing Verilog/SystemVerilog test cases with minimal assistance from designers.
  • Functional simulation using Verilog/SystemVerilog.
  • Scripting languages such as Shell, Perl, TCL, and Python for automation of design database qualification and packaging.
  • Familiarity with Power Flow (UPF/CPF).
  • Collaboration with IP-development teams to facilitate high-quality releases.
  • Maintaining package and release timelines for various projects.
  • Bug reporting and resolution closure with IP providers.
  • Ability to debug synthesis/timing analysis constraints, reports, and logs.

The successful candidate will also possess the following skills:

  • Able to learn new tools/flows and develop methodology if needed.
  • Build and maintain close relationships with Designers and Application Engineers.
  • Fastidious approach to building automated processes.
  • Strong interpersonal and relationship-building skills.

Desirable Qualifications

  • Familiarity with SerDes/DDR/other Design-IPs and Analog design flows.
  • Familiarity with IP release and tracking management systems.


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