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Principal RTL Design Engineer

3 weeks ago

Bengaluru, Karnataka, India Cadence Full time
About Cadence

Cadence is a leading provider of electronic design automation (EDA) software and intellectual property. We are committed to helping our customers deliver innovative electronic products faster and more efficiently.

Job Description

We are seeking an experienced Principal RTL Design Engineer to join our team in SerDes IP development. The ideal candidate will have a strong background in front-end design for high-performance SerDes IPs across various technology nodes (>100G rates).

The successful candidate will be responsible for synthesizing complex SerDes IPs, executing Static Timing Analysis (STA), and defining timing constraints to ensure robust timing closure. They will also implement low-power design techniques using CPF/UPF and optimize designs for performance, area, and power.

We are looking for someone with 10+ years of experience in front-end RTL design and synthesis for high-speed interfaces and SerDes IPs. Proficiency in Verilog/SystemVerilog, Synthesis tools (DC, Genus, or equivalent), and timing analysis tools (PT, Tempus, etc.) is required. Strong expertise in DFT, ATPG, and structural testing techniques is also necessary.