Principal Interconnect Fabric Microarchitecture
4 weeks ago
Founded by highly respected Silicon Valley veterans - with its design centers established in Santa Clara, California. / Hyderabad
A US based well-funded product-based startup looking for Highly talented ASIC / RTL / Logic Design Engineers for the following roles.
- Principal Interconnect Fabric Microarchitecture & IP Logic Design Engineer
- we are looking for candidates with Arm IP background like: CHI, CMN, Arm CPUs, etc
Responsibilities
- Work in designing high performance Interconnects/Fabrics/NoCs
- Architectural exploration for power, performance and area efficient interconnect systems
- Microarchitecture development for PPA efficiency and creating microarchitecture specification documents
- Perform efficient RTL coding in Verilog or System Verilog for IP development
- Collaborate with performance analysis team to design, correlate and enhance performance metrics
- Collaborate with pre-silicon verification, emulation and post silicon validation in developing validation infrastructure and making sure design is functionally correct
- Collaborate with physical design team in synthesis, place and route planning, and to make sure design meets area and frequency requirements
- Work with cross-functional engineering teams to ensure the design is of high quality
Requirements
- Master’s, PhD or bachelor’s degree in relevant subject area
- Thorough knowledge of high performance coherent and non-coherent interconnects
- Prior experience with one more on chip interconnect protocols like CHI, ACE, AXI, TileLink or their equivalent X86 protocols
- Knowledge of on-chip network topologies like Mesh, Crossbar, Ring, etc
- Prior experience with CPU, GPU or System caches and Coherency protocols
- Understanding of high performance and low power microarchitecture techniques and logic design principles
- Proficiency in Verilog or System Verilog coding, and ability to identify PPA efficiency enhancements in RTL
- Experience with front end ASIC design EDA tools like simulators, waveform debuggers,
- IDEs, etc
Contact:
Uday
Mulya Technologies
muday_bhaskar@yahoo.com
"Mining The Knowledge Community"
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Principal interconnect fabric microarchitecture
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